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Details, datasheet, quote on part number:MT9300AL
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Datasheet text preview:
MT9300
Multi-Channel Voice Echo Canceller Advance Information
Features
· Independ e n t multiple channels echo cancellat i o n ; from 32 channels of 64ms to 16 channels of 128ms with the ability to mix channels at 128ms or 64ms in any combination Independ e n t Power Down mode for each group of 2 channels for power management Confor m s to ITU-T G.165 and G.168 Recommendations Field proven, high quality performance Compatibl e to ST-BUS and GCI interface at 2Mb/s serial PCM PCM coding, µ/A-Law ITU-T G.711 or sign magnitude Per channel Fax/Modem G.164 2100Hz or G.165 2100Hz phase reversal Tone Disable Per channel echo canceller parameters control Transpare n t data transfer and mute Non-Line a r processor with high quality subjective performance Protectio n against narrow band signal d i ve r g e n c e Offset nulling of all PCM channels 10 MHz or 20 MHz master clock operation 3.3 Volts operation with 5-Volt tolerant inputs No external memory required Non-mul t i p l exe d microprocessor interface IEEE-114 9 . 1 (JTAG) Test Access Port
VDD VSS
DS5030 ISSUE 2 May 1999
O rd e r i n g Information MT9300AL 160-Pin MQFP - 4 0 °C to +85°C
· · · · · · · · · · · · · · · ·
Applications
· · · · · · Vo ic e over IP network gateways Vo ic e over ATM, Frame Relay T 1 / E 1 / J 1 multichannel echo cancellation W ir e le s s base stations E c h o Canceller pools DCM E , satellite and multiplexer systems
Description
The MT9300 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The MT9300 architecture contains 16 groups of two echo cancellers (ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. This provides 32 channels of 64 milliseconds to 16 channels of 128 milliseconds echo cancellation or any combination of the two configurations. The MT9300 supports ITU-T G.165 and G.164 tone disable requirements.
ODE
Echo Canceller Pool
Rin Sin MCLK Fsel PLL Serial to Parallel
Group 0
ECA/ECB
Group 1
ECA/ECB
Group 2
ECA/ECB
Group 3
ECA/ECB
Parallel to Serial
Rout Sout
Group 4
ECA/ECB
Group 5
ECA/ECB
Group 6
ECA/ECB
Group 7
ECA/ECB
Group 8
ECA/ECB
Group 9
ECA/ECB
Group 10
ECA/ECB
Group 11
ECA/ECB
Group 12
ECA/ECB C4i F0i Timing Unit
Group 13
ECA/ECB
Group 14
ECA/ECB
Group 15
ECA/ECB
Note: Refer to Figure 3 for Echo Canceller block diagram
IC0
RESET Microprocessor Interface Test Port
DS CS R/W A10-A0 DTA
D7-D0
IRQ TMS TDI TDO TCK TRST
Fi gur e 1 - Functional Block Diagram
1
MT9300
NC ODE Sout Rout VSS NC NC NC NC VDD NC NC NC NC VDD Sin Rin F0 i C4i VDD IC0 IC0 IC0 IC0 VSS 117 115 NC NC NC NC VSS VSS IC0
Advance Information
VSS NC NC NC NC NC VSS
NC
IC0 IC0 NC VDD NC NC NC NC NC NC NC NC IC0 IC0 IC0 NC NC VSS VSS MCLK VDD VDD Fsel IC0 IC0 PLLVSS PLLVDD VSS VSS NC NC TMS TDI TDO TCK TRST IC0 RESET VDD NC
119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 1
113
111
109
107 105 103
101
99
97
95
93
91
89
87
85
83
81 79 77 75 73 71 69 67 65 63 NC VDD NC VSS VSS NC NC NC NC NC NC NC NC NC NC NC NC VDD NC NC NC IC0 VSS IC0 A10 A9 A8 VDD A7 A6 A5 A4 VSS A3 A2 A1 A0 VDD NC NC
160 Pin MQFP
61 59 57 55 53 51 49 47 45 43 41
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
NC NC NC DTA R/W CS DS IRQ VDD
Pin Description
Pin #
1, 2, 17, 27, 37, 38, 48, 58, 76, 77, 81, 87, 98, 108, 118, 119, 138, 139, 148, 149 8, 22, 32, 43, 53, 63, 79, 93, 103, 113, 124, 141, 142, 159 57, 59, 114, 115, 116,117, 120, 121,122, 133, 134, 135, 144, 145, 157,
2
VSS
NC NC NC NC NC VSS
Fi gure 2 - Pin Connections
D3 D2 D1 D0 VSS
D7 D6 D5 D4 VDD
NC NC NC NC VSS
NC NC NC NC VDD
VSS
NC NC VSS
Name VSS Ground.
Description
VDD
Positive Power Supply. Nominally 3.3 volt.
IC0
Internal Connection. These pins must be connected to VSS for normal operation.
Advance Information
Pin Description (continued)
Pin #
3 to 7, 14 to 16, 28 to 31, 33 to 36, 39 to 42, 60 to 62, 64 to 75, 78, 80, 82 to 86, 88 to 92, 94 to 97, 99 to102, 104, 123, 125 to 132, 136, 137, 150,151,160
MT9300
Name NC
Description No connection. These pins must be left open for normal operation.
9
IRQ
Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1K typical) is required at this output. Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1K typical) is required at this output. Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. Output Drive Enable (Input). This input pin is logically AND'd with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled. When the ODE bit is low or the ODE input pin is low, the Rout and Sout ST-BUS outputs are high impedance. Send PCM Signal Output (Output). Port 1 TDM data output streams. Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Input (Input). Port 1 TDM data input streams. Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout).
10 11 12 13
DS CS R/W DTA
18, 19, 20, 21, 23, 24, 25, 26
44, 45,46, 47,49, 50, 51,52,54, 55, 56
D0 - D3, D4 - D7 A0 - A10
105
ODE
106
Sout
107 109
Rout Sin
110
Rin
111
F0i
112
C4i
3
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