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Details, datasheet, quote on part number:NP2S
 
 
Part:NP2S
Description:Satellite Zero if QPSK Tuner ic
Company:Mitel Networks Corporation
Datasheet:Download NP2S datasheet   File size : 537 kB
Request For quote:  Find where to buy NP2S
 



Datasheet text preview:
SL1925
Satellite Zero IF QPSK Tuner IC Preliminary Information
DS4955 Issue - 2.0 March 1999
Features
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Ordering Information
SL1925/KG/NP2S (Tubes) SL1925/KG/NP2T (Tape and Reel)
q q q q q q
q
Single chip system for direct quadrature down conversion from L-band High signal handling capability for minimum external component count application, requires external RF AGC of 30dB Compatible with DSS and DVB system requirements Excellent gain and phase match up to 30MHz baseband High output referred linearity for low distortion and multi channel application Fully balanced low radiation design Integral RF AGC amplifier Two selectable varactor tuned local oscillators with buffered output for driving external synthesiser loop ESD protection (Normal ESD handling procedures should be observed)
Description
The SL1925 is a wideband quadrature converter operating from 950 to 2150 MHz, intended primarily for application in satellite tuners. The device contains all elements necessary, with the exception of local oscillator sustaining network, to fabricate a high performance I(n-phase) & Q(uadrature) phase splitter and downconverter optimised for systems containing RF AGC gain control. The device allows for systems containing higher power analog interferers. For most applications RF tunable filtering is not essential. The SL1925 is optimised for use with a low phase noise synthesiser, a range of which are available from Mitel Semiconductor. This will form a complete front end tuner function for digital satellite receiver systems utilising DSP derotation recovery. The device includes a very high signal handling front end with AGC, this provides for gain control, reference local oscillator with output buffer, phase splitter with I and Q mixers and baseband buffer amplifiers with external interstage filtering.
Applications
Satellite receiver systems q Data communications systems
q
SL1925
Preliminary Information
OPFI Vcc PSout PSoutb Vee Tanks Tanksb Vee Tankv Tankvb Vee NC Vcc OPFQ
14
1
28
Vee IPFI Vee Iout LOsel Vcc RF RFB Vee AGC Qout Vee IPFQ Vee
15
NP28
Figure 1 Pin connections
25 AGC 19 AGC SENDER
Iout
27
IPFI
1
OPFI
RF RFB
22 21
0 DEG
14
OPFQ
90 DEG 16 IPFQ
Tankv Tankvb
9 10
vcov
18
Qout
Tanks Tanksb
6 7
vcos DIVIDE BY 2
FREQUENCY AGILE PHASE SPLITTER
3 4
PSout PSoutb Vcc Vee
LOsel
24
2, 13, 23 5, 8, 11, 15, 17, 20, 26, 28
Figure 2 Block diagram
2
Preliminary Information
Quick Reference Data
Characteristic Operating range Input noise figure, DSB, maximum gain, 1500MHz Maximum conversion gain (assuming 6dB filter loss) Minimum conversion gain (assuming 6dB filter loss) IP32T input referred Converter input referred IM3, two tones at 97dBµV IP22T input referred P1dB input referred Baseband amplifier Output limit voltage Gain match up to 22 MHz Phase match up to 22 MHz Gain flatness up to 22 MHz Local oscillator phase noise across entire 950MHz to 2150MHz band: SSB @ 10 kHz offset Table 1
SL1925
950-2150 19 >55 <20 113 30 140 103 2.0 0.2 0.7 0.5 80
Units MHz dB dB dB dBuV dBc dBuV dBuV V dB deg dB dBc/Hz
Functional Description
The SL1925 is a wideband direct conversion quadrature downconverter optimised for application in satellite receiver systems. A block diagram is given in Figure 2 and shows the device to include a broadband RF preamplifier with AGC control, two oscillator sustaining amplifiers, a frequency agile 90° phase splitter, I Q channel mixers and I Q channel baseband amplifiers. The only additional elements required are an external tank circuit for each oscillator, and baseband interstage filters. To fabricate a complete tuner an RF AGC stage offering +20dB to -10 dB of gain range and a 2.2 GHz PLL frequency synthesiser are also required. An example application is shown in Figure 16. In normal application the first satellite IF frequency of typically 950 to 2150 MHz is fed via the tuner RF AGC stage to the RF preamplifier, which is optimised for i m p e d a n c e match and signal handling. The RF preamplifier is designed such that no tracking RF filter is required and also allows for analog interferers at up to 10 dB higher amplitude. The converter RF input impedance is shown in Figure 5. The amplifier signal is then fed to an AGC stage providing a minimum of 35dB AGC control, which together with the RF attenuator provides a possible overall tuner dynamic range of 65dB, to allow for normal operating dynamic range and MCPC systems. The signal is then split into two balanced channels to drive the I and Q mixers. The AGC characteristic, and gain variation of IIP3, IIP2, P1dB and NF are contained in Figs. 6, 7, 8, 9 and 10 respectively.
The required 950MHz to 2150MHz I and Q reference LO frequencies for quadrature direct conversion are generated by the on board oscillators named `vcos' and `vcov', and the phase splitter. Oscillator `vcos' operates nominally from 1900MHz to 3000MHz and is then divided by two to provide 950MHz to 1500MHz. Oscillator `vcov' operates nominally from 1400MHz to 2150MHz. Only one oscillator is active at any time and selection is made within the phase splitter under the control of the LOsel input. Each oscillator uses an external varactor tuned resonant network optimised for low phase noise with a single varactor line control. A recommended application circuit for the oscillators is shown in Figure 4. The LO from the phase splitter drives a buffer whose outputs `PSout' and `PSoutb' can be used for driving an external PLL control loop for the VCO's. The typical LO phase noise is shown in Figure 11. The mixer outputs are coupled to baseband buffer outputs `OPFI' and `OPFQ' which drive external band limit filters. The output impedance of these buffers is contained in Figure 12. The outputs of the filters are then connected to the inputs `IPFI' and `IPFQ' of the baseband channel amplifiers. The outputs `Iout' and `Qout' provide for a low impedance drive and can be used with a maximum load as in Figure 3. The output impedance of this section is contained in Figure 13. An example filter for application with 30MS/s systems is contained in Figure 14. All port peripheral circuitry for the SL1925 is shown in Figure 15a and 15b. The typical key performance data at 5V Vcc and 25°C ambient are shown in the `QUICK REFERENCE DATA' of Table 1.
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