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Details, datasheet, quote on part number:NWK933
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| Part: | NWK933 |
| Category: | Communication => Network => Ethernet/DS1/E1 (T1/E1) |
| Description: | 3.3v 10/100 Fast Ethernet Transceiver to Mii |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download NWK933 datasheet File size : 145 kB |
| Request For quote: | Find where to buy NWK933
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Datasheet text preview:
NWK933
NWK933
3.3V 10/100 Fast Ethernet Transceiver to MII
DS5029 Issue no 2.1 May 1999
Features Odering Information
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Integrated 10/100 Mbps Ethernet in a Single Chip Solution Single 3.3V Power Supply Half Duplex and Full Duplex in both 10BASE-T and 100BASE-TX Full MII for a Glueless MAC Connection Extended Register Set Integrated 10BASE-T Transceivers and Receive / Transmit Filters Integrated Adaptive Equaliser and Base Line Wander Correction (for FDDI Killer Packet) Full Auto-Negotiation Support for 10BASE-T and 100BASE-TX both Half and Full Duplex Link Status Change Interrupt Parallel Detection for Supporting Non Auto Negotiation in Legacy Link Partners Low Dynamic Current Deep Sleep Low Power Mode <1mA Internal Power on Reset 64 pin 1mm thick TQFP Package Single Magnetics for 10BASE-T and 100BASE-TX Operation for a Single RJ45 Connector Support for Flow Control 802.3 Specification Integrated 6 LED Driver
NWK933/CG/TP1N
Low External Component Count Loop-back mode for diagnostics q Intelligent power management (auto shutdown, auto wake) q Low Transmit Jitter
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Description
The NWK933 is a single chip 3.3V CMOS physical layer solution from MII to the magnetics. It is designed f o r 10BASE-T and 100BASE-TX Ethernet, based on the IEEE 802.3 specifications.
The NWK933 is compatible with the Auto Negotiation section of IEEE 802.3u and provides all the support needed for the 802.3 Full duplex specification.
Switch or MAC
NWK933
Isolation Magnetics
RJ45
Figure 1 System block diagram
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NWK933
64 TX_CLK 63 TX03 62 TXD2 61 TXD1 60 TXD0 59 RX_ER 58 RXD3 57 RXD2 56 RXD1 55 RXD0 54 DVDD2 53 RX_CLK 52 DGND2 51 RX_DV 50 CRS 49 COL
SUBGND2 1 TX_ER 2 DGND1 3 TX_EN 4 LNKST 5 ACTST 6 COLST 7 DVDD1 8 RXVDD3 9 RXGND3 10 FDST 11 SPDST 12 PA4 13 RESETN 14 RXVDD2 15 RXGND2 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MINT DVDD3 MDC MDIO DGND3 RefCLK OSCVDD XTAL1 XTAL2 OSCGND TXGND4 TXVDD4 TXREF100 TXREF10 TXVDD3 TXGND3
PA3 17 RXGND1 18 RXIP 19 RXIN 20 RXVDD1 21 ANEN 22 TXOP 23 TXVDD2 24 TXGND2 25 TXGND1 26 TXVDD1 27 TXON 28 PA2 29 PA1 30 PA0 31 SUBGND1 32
TP64
Figure 2Pin connections
Functional Description
The NWK933 has three basic modes of operation: 10BASE-T, 100BASE-TX and LOW POWER modes. The Control block is designed to manage these modes by starting and stopping the 10M and 100M transceivers in a well-controlled manner such that no spurious signals are output on either the MII or twisted-pair interfaces. Furthermore, it continuously monitors the behaviour of the transceivers and takes corrective action if a fault is detected. Other modes described herein are repeater mode and reset mode.
10Base-T Operation 10Mb/s Data Transfer on the MII
10Mb/s data is transferred across the MII with clock speeds of 2.5MHz. The MAC outputs data to the NWK933 via the MII interface, on the TXD[3:0] bus. This data is synchronised to the rising edge of TX_CLK. To indicate that there is valid data for transmission on the MII, the MAC sets the TX_EN signal active. This forces the NWK933 device to take in the data on the TXD[3:0] bus. This is serialised and directly encoded as Manchester data, before being output on the TXOP/ TXON differential output for transmission through 1:Ö2 magnetics and onto the twisted-pair. The transmit current is governed by the current through the TXREF10 pin, which must be grounded through a resistor as described in "External Components".
25MHz Reference Clock
The NWK933 requires a 25MHz +/-100ppm timing reference for 802.3 compatible operation. This may be supplied either from the integrated oscillator or from an external source. When the integrated oscillator is used, a suitable crystal must be connected across the XTAL1 & XTAL2 pins (see "External Components") and REFCLK must be tied low. When an external source is used, it must be input to the REFCLK pin a n d XTAL1 must be tied low. XTAL2 must be unconnected.
RX10 Clock Recovery
The NWK933 employs a digital delay line controlled by the 100MHz Synthesizer DLL to derive a sampling clock from the incoming signal. The recovered clock runs at twice the data rate (nominally 20MHz). When a signal is received from the Signal Detect block, it is used to strobe Link Pulses and Manchester encoded serial data.
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NWK933
The Manchester data stream will be decoded into a 4bit parallel data bus, RXD[3:0]. The RXD bus is clocked out on RX_CLK rising. The NWK933 must detect the first 4 bits of pre-amble before RX_DV is set high. When RX_DV is high, any Manchester coding violation will set RX_ER high. RX_DV is reset by a continuous sequence of zeroes, or by the end-of-packet IDLE terminator (11 11 00 00). Whilst RX_DV is low, the data is invalid.
RX10 Latency
When connected to appropriate magnetics the latency through the RX10 path is less than 6BT (600ns). This timing is measured from the input of the receive magnetics to the rising edge of RX_CLK. The RX10 path may ignore up to three Manchester encoded bits at the start of data reception (802.3 allows up to 5 bits).
100MHz Synthesizer
This synthesizer employs a delay-locked loop (DLL) to generate a 100MHz timing reference from the 25MHz reference clock. This 100MHz reference is used by the 10BASE-T transmit and receive functions and is divided by 5 to provide a 20MHz data strobe. The 20MHz clock is used to derive the 2.5 MHz TX_CLK in 10BASE-T mode. The synthesizer is disabled when not in 10BASE-T mode.
100Base-TX Operation
100Mb/s Data Exchange on the MII Interface 100Mb/s data is transferred across the MII with clock speeds of 25MHz. The MAC outputs data to the NWK933 via the MII interface, on the TXD[3:0] bus. This data is synchronised to the rising edge of TX_CLK. To indicate that there is valid data for transmission on the MII, the MAC sets the TX_EN signal active. This forces the NWK933 device to take in the data on the TXD[3:0] bus and replace the first octet of the MAC preamble with Start-of-Stream Delimiter (SSD) symbols to indicate the start of the Physical Layer Stream. When the data transfer across the MII is complete, the MAC deasserts the TX_EN signal and the NWK933 adds End-of-Stream Delimiters (ESD) symbols onto the end of the data stream. The complete data stream (the Physical Layer Stream) is encoded from 4 bits into 5 bits, scrambled, converted to MLT3 and driven to the TXOP and TXON pin differentially. The TX100 path is disabled when not in 100BASE-TX mode and, with the exception of the RX100 Signal Detect, the RX100 Receive Path is disabled when not in 100BASE-TX mode.
TX10 Pulse Shaper & Filter
The Pulse Shaper & Filter employs a digital Finite Impulse Response filter (FIR) to pre-compensate for l i n e distortion and to remove high frequency components in accordance with the 802.3 Standard. The Pulse Shaper & Filter is disabled when not in 10BASE-T mode.
TX10 Latency
When connected to appropriate magnetics the latency through the TX10 path is less than 2BT (200ns) for data transmissions. This timing is measured from the rising edge of TX_CLK to the output of the transmit magnetics. The TX10 path will not transmit up to the f i r s t two Manchester encoded bits of a data transmission, as permitted by the 802.3 Standard.
125MHz Synthesizer
This synthesizer employs a phase-locked loop (PLL) to generate a 125MHz timing reference from the 25MHz reference clock. This 125MHz reference is used by the 100BASE-TX transmit function and is divided by 5 to provide a 25MHz data strobe on TX_CLK. TX_CLK is frequency and phase locked to the 25MHz reference with a small phase offset. The synthesizer is disabled when not in 100BASE-TX mode.
RX10 Filter & RX10 Signal Detect
These blocks work in unison to remove noise and to block signals that do not achieve the voltage levels specified in 802.3. Signals that do not achieve the required level are not sampled in the Clock Recovery block and are not passed to the outputs.
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