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Part: SL74HC4046N
Category:
Description: Phase-locked Loop
Company: System Logic Semiconductor
Datasheet: Download SL74HC4046N datasheet File size : 170 kB
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SL74HC4046
Phase-Locked Loop
High-Performance Silicon-Gate CMOS
The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC4046 phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain opamp DEM OUT. The comparators have two common signal inputs, COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1OUT and maintains 90 degrees phase shift at the center frequency between SIGIN and COMPIN signals (both at 50% duty cycle). Phase comparator 2 ORDERING INFORMATION (with leading-edge sensing logic) provides digital error signals PC2OUT SL74HC4046N Plastic and PCPOUT and maintains a 0 degree phase shift between SIGIN and SL74HC4046D SOIC COMPIN signals (duty cycle is immaterial). The linear VCO produces an TA = -55° to 125° C for all packages output signal VCOOUT whose frequency is determined by the voltage of input VCOIN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEM OUT with an external resistor is used where the VCOIN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all on-amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control. · Low Power Consumption Characteristic of CMOS Device PIN ASSIGNMENT · Operating Speeds Similary to LS/ALSTTL · Wide Operating Voltage Range: 3.0 to 6.0 V · Low Input Current: 1.0 µA Maximum (except SIGIN and COMPIN) · Low Quiescent Current: 80 µA Maximum (VCO disabled) · High Noise Immunity Characteristic of CMOS Devices · Diode Protection on all Inputs
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN PC3OUT VCC
Name and Function Phase Comparator Pulse Output Phase Comparator 1 Output Comparator Input VCO Output Inhibit Input Capacitor C1 Connection A Capacitor C1 Connection B Ground (0 V) VSS VCO Input Demodulator Output Resistor R1 Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply Voltage
System Logic Semiconductor
SLS
SL74HC4046
MAXIMUM RATINGS *
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260
Unit V V V mA mA mA mW °C °C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) VCO only DC Supply Voltage (Referenced to GND) NON-VCO DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 3.0 2.0 0 -55 0 0 0 Max 6.0 6.0 VCC +125 1000 500 400 Unit V V V °C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V C). C Unused outputs must be left open.
SLS
System Logic Semiconductor
SL74HC4046
[Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±3.0 ±7.0 ±18.0 ±30.0 ±0.5 85 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±4.0 ±9.0 ±23.0 ±38.0 ±5.0 125 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±5.0 ±11.0 ±27.0 ±45.0 ±10 µA V Unit
VIH
Minimum High-Level Input Voltage DC Coupled SIGIN , COMPIN Maximum Low -Level Input Voltage DC Coupled SIGIN , COMPIN Minimum High-Level Output Voltage PCPOUT, PCn OUT
VOUT= 0.1 V or VCC-0.1 V IOUT 20 µA
2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0
V
VIL
VOUT=0.1 V or VCC-0.1 V IOUT 20 µA
V
VOH
VIN=VIH or VIL IOUT 20 µA VIN= VIH or VIL IOUT 4.0 mA IOUT 5.2 mA
V
VOL
Maximum Low-Level Output Voltage Qa -Qh PCPOUT, PCn OUT
VIN=VIH or VIL IOUT 20 µA VIN= VIH or VIL IOUT 4.0 mA IOUT 5.2 mA
IIN
Maximum Input Leakage Current SIGIN , COMPIN Maximum Three-State Leakage Current PC2OUT Maximum Quiescent Supply Current (per Package) (VCO disabled) Pins 3,5 and 14 at VCC Pin 9 at GND; Input Leacage at Pin 3 and 14 to be excluded
VIN=VCC or GND
IOZ
Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND VIN=VCC or GND IOUT=0µA
µA
ICC
6.0
4.0
40
160
µA
SLS
System Logic Semiconductor
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