Details, datasheet, quote on part number: PE97632ES
Description3.2 GHz Delta-sigma Modulated Fractional-n Frequency Synthesizer for Low Phase Noise Applications
DatasheetDownload PE97632ES datasheet


Features, Applications

Peregrine's is a high performance fractional-N PLL capable of frequency synthesis to 3.2 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with the existing commercial space PLLs. The PE97632 features a 10/11 dual modulus prescaler, counters, a delta sigma modulator, and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial interface or directly hard-wired. The PE97632 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. Fabricated in Peregrine's patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE97632 offers excellent RF performance and intrinsic radiation tolerance. 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications Features 3.2 GHz operation ÷10/11 dual modulus prescaler Phase detector output Serial or Direct mode access Frequency selectivity: Comparison frequency / 218 Low power 3.3 V Rad-Hard Ultra-low phase noise 68-lead CQFJ

©2006 Peregrine Semiconductor Corp. All rights reserved. Page of 16

Input Downbond (Note 1) R Counter bit0 (LSB). R Counter bit1. R Counter bit2. R Counter bit3. R Counter bit4. R Counter bit5 (MSB). K Counter bit0 (LSB). K Counter bit1. Ground Digital core VDD. K Counter bit2. K Counter bit3. K Counter bit4. K Counter bit5. K Counter bit6.

©2006 Peregrine Semiconductor Corp. All rights reserved. Page of 16

Input (Note 1) Downbond K Counter bit7. K Counter bit8. K Counter bit9. K Counter bit10. K Counter bit11. K Counter bit12. K Counter bit13. K Counter bit14. K Counter bit15. K Counter bit16. K Counter bit17 (MSB). Digital core VDD. Ground M Counter bit0 (LSB). M Counter bit1. M Counter bit2 M Counter bit3. M Counter bit4.

Direct Serial Direct Serial Direct Serial Direct Serial Direct Both Direct
33 S_WR M5 34 SDATA M6 35 SCLK A1 39 E_WR A2 A3 DIRECT Pre_en VDD GND

Serial load enable input. While S_WR is "low", Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR or Hop_WR rising edge. M Counter bit5. Binary serial data input. Input data entered MSB first. M Counter bit6. Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR "low") or the 8-bit enhancement register (E_WR "high") on the rising edge of Sclk. M Counter bit7. M Counter bit8 (MSB). A Counter bit0 (LSB). A Counter bit1. Enhancement register write enable. While E_WR is "high", Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. A Counter bit2. A Counter bit3 (MSB). Direct mode select. "High" enables direct mode. "Low" enables serial mode. Prescaler enable, active "low". When "high", Fin bypasses the prescaler. Digital core VDD. Ground

©2006 Peregrine Semiconductor Corp. All rights reserved. Page of 16


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