Electrical and Electronics Engineering publications abstract of: 12-2017 sorted by title, page: 0

» $H_{infty }$-Based Nonlinear Observer Design for State of Charge Estimation of Lithium-Ion Battery With Polynomial Parameters
Abstract:
This paper focuses on the state-of-charge (SOC) estimation of the Lithium-ion battery in electric vehicles based on an -based nonlinear observer. First, the second-order RC equivalent circuit model is introduced by utilizing the physical behavior of the battery. Then, the parameters in the second-order RC model are identified as polynomial functions with respect to SOC. Meanwhile, the battery model with constant parameters is also introduced for comparison. Due to that the battery model is undetectable, an one-sided Lipschitz condition is proposed to ensure that the nonlinear function in output equation can play a positive role in the observer design. After that, a nonlinear observer design criterion is presented based on the method, which is formulated as linear matrix inequalities. Compared with existing nonlinear observer-based SOC estimation methods, the proposed observer design criterion does not depend on any estimates of the unknown variables. Consequently, the convergence of the proposed nonlinear observer is guaranteed for various operating conditions. Finally, one static and three dynamic operation conditions are given to show the efficiency of the proposed nonlinear observer by comparing with the classic extended Kalman filter and the nonlinear observer for constant parameters.
Autors: Qiao Zhu;Liang Li;Xiaosong Hu;Neng Xiong;Guang-Di Hu;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Dec 2017, volume: 66, issue:12, pages: 10853 - 10865
Publisher: IEEE
 
» ${Z}^{textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration
Abstract:
2-D numerical simulations are used to demonstrate the -FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.
Autors: Carlos Navarro;Meng Duan;Mukta Singh Parihar;Fikru Adamu-Lema;Stefan Coseman;Joris Lacord;Kyunghwa Lee;Carlos Sampedro;Binjie Cheng;Hassan El Dirani;Jean-Charles Barbe;Pascal Fonteneau;Seong-Il Kim;Sorin Cristoloveanu;Maryline Bawedin;Campbell Millar
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2017, volume: 64, issue:12, pages: 4904 - 4909
Publisher: IEEE
 
» “All Good Things Must Come to an End”
Abstract:
In her final message as editor in chief of IEEE Pervasive Computing, Maria Ebling looks to the future and introduces who will come next as she passes the baton.
Autors: Maria R. Ebling;
Appeared in: IEEE Pervasive Computing
Publication date: Dec 2017, volume: 16, issue:4, pages: 4 - 6
Publisher: IEEE
 
» 1.1-kW Peak-Power Dissipative Soliton Resonance in a Mode-Locked Yb-Fiber Laser
Abstract:
We report an ytterbium-doped all-fiber laser generating dissipative soliton resonance (DSR) pulses with kilowatt-level peak power. The laser cavity was constructed with all-10/125 large-mode-area fibers to alleviate excessive nonlinear effects caused by high peak power. DSR pulse breaking and Raman-induced instability are avoided by carefully placing the fiber sections. Numerical and experimental investigation of high-peak-power DSR laser mode-locked with nonlinear optical loop mirrors is presented. Up to 1.66 W, 161-nJ energetic pulses are obtained without pulse-breaking. In particular, the laser generates pulses with 48–146 ps tunable pulse duration and an almost fixed peak power as high as 1.1 kW. To the best of our knowledge, this letter presents the first demonstration of DSR pulses with kilowatt-level peak power in mode-locked fiber lasers.
Autors: Jun-Hao Cai;Sheng-Ping Chen;Jing Hou;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2017, volume: 29, issue:24, pages: 2191 - 2194
Publisher: IEEE
 
» 1.29-W/mm2 23-dBm 66-GHz Power Amplifier in 55-nm SiGe BiCMOS With In-Line Coplanar Transformer Power Splitters and Combiner
Abstract:
This letter presents a four-way parallel–series power amplifier (PA) in 55-nm SiGe BiCMOS with in-line coplanar transformers for output power combining, and input/interstage power splitting. The in-line geometry allows an area efficient impedance matching design and an effective input signals routing to the individual PA stages without phase mismatch. The measurements show that the PA delivers a maximum output power of 23.4 dBm, an output-referred P1dB of 20 dBm, a gain of 23.8 dB, and a maximum power added efficiency of 12.5%, at 66 GHz, with a record power density (output power/active area) of 1.29 W/mm2 among PAs on silicon technologies operating beyond 40 GHz.
Autors: Domenico Pepe;Domenico Zito;Andrea Pallotta;Luca Larcher;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2017, volume: 27, issue:12, pages: 1146 - 1148
Publisher: IEEE
 
» 1.96-μm Tm:YAG Ceramic Laser
Abstract:
We have demonstrated an efficient diode-end-pumped continuous-wave Tm:YAG ceramic laser at 1962 nm using a compact two-mirror cavity. The laser oscillation at 1962 nm was realized by increasing the cavity loss at 2016 nm to limit oscillation with the strongest laser gain. For comparison, two different output couplers were used to build single wavelength lasers operating at 1962 and 2016 nm. A laser output power of 2.06 W at 1962 nm was achieved for an absorbed pump power of 6.59 W with the laser ceramic temperature maintained at 15 °C. The corresponding slope efficiency and conversion efficiency were calculated to be 37.8% and 31.3%, respectively. In contrast, the maximum output power at 2016 nm was approximately 3.47 W under the same conditions. The 1962 nm laser has potential application in the analysis of CO2 and HBr molecular gases.
Autors: Haiyong Zhu;Yongchang Zhang;Jing Zhang;Yaoju Zhang;Yanmin Duan;Xiukai Ruan;Jian Zhang;Dingyuan Tang;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2017, volume: 9, issue:6, pages: 1 - 7
Publisher: IEEE
 
» 15-kV/40-A FREEDM Supercascode: A Cost-Effective SiC High-Voltage and High-Frequency Power Switch
Abstract:
High-voltage wide bandgap semiconductor devices such as the 15 kV SiC mosfet have attracted great attention because of their potential applications in high-voltage and high-frequency power converters. However, these devices are not commercially available at the moment, and their high cost due to expensive material growth and fabrication may limit their widespread adoption in the future. In this paper, a 15-kV 40-A SiC three-terminal power switch, the Future Renewable Electric Energy Delivery and Management (FREEDM) supercascode, is reported for the first time, which is based on a series connection of 1.2-kV SiC power devices. Compared with the monolithic 15-kV SiC mosfet, the FREEDM supercascode demonstrates obvious advantages in cost and thermal conductivity. The design and voltage-balancing mechanism of the FREEDM supercascode are introduced, and the performance including the voltage balancing, conduction characteristics over a wide range of temperatures, and dynamic switching performance, is analyzed. The FREEDM supercascode's low cost and excellent thermal dissipation capability will facilitate early applications of SiC in very high voltage and high frequency power converters.
Autors: Xiaoqing Song;Alex Q. Huang;Soumik Sen;Liqi Zhang;Pengkun Liu;Xijun Ni;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Dec 2017, volume: 53, issue:6, pages: 5715 - 5727
Publisher: IEEE
 
» 2- $mu$ m Repetition-Rate Tunable (1–6 GHz) Picosecond Source
Abstract:
We have for the first time experimentally demonstrated a high repetition-rate picosecond fiber laser source at 2 by a spectrally masked phase modulation technique, where a phase modulator driven by a sinusoidal RF signal and a fiber Bragg grating are used to convert the output of a 2- continuous-wave single-longitudinal-mode diode to a picosecond pulse train. The repetition-rate of this laser source can be continuously and flexibly tuned from 1 to 6 GHz by simply changing the RF signal. We achieved a shortest pulse width of ~60 ps and a high SNR of >75 dB at an operating frequency of 6 GHz. The simplicity and robustness of such a picosecond laser as well as the ability to synchronize with an external trigger make it a highly useful source for 2- high speed optical data processing, communications, and metrology.
Autors: Jiarong Qin;Yafei Meng;Wenbin Gao;Yao Li;Labao Zhang;Jinlong Xu;Shining Zhu;Fengqiu Wang;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2017, volume: 29, issue:24, pages: 2234 - 2237
Publisher: IEEE
 
» 2-D Drift-Diffusion Simulation of Organic Electrochemical Transistors
Abstract:
A 2-D device model of the organic electrochemical transistor is described and validated. Devices with channel length in range 100 nm–10 mm and channel thickness in range 50 nm– are modeled. Steady-state, transient, and AC simulations are presented. Using the realistic values of physical parameters, the results are in good agreement with the experiments. The scaling of transconductance, bulk capacitance, and transient responses with device dimensions is well reproduced. The model reveals the important role of the electrical double layers in the channel, and the limitations of device scaling.
Autors: Marek Zdzisław Szymański;Deyu Tu;Robert Forchheimer;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2017, volume: 64, issue:12, pages: 5114 - 5120
Publisher: IEEE
 
» 2.3-GHz HBT Power Amplifier With Parallel-Segmented On-Chip Autotransformer
Abstract:
A parallel-segmented primary autotransformer is proposed to optimize passive efficiency as well as impedance transformation ratio. In addition, a corresponding equivalent lumped model has been proposed and shows a good agreement with electromagnetic -simulated and measured data. This paper also presents a fully integrated HBT power amplifier with a parallel-segmented primary autotransformer to obtain watt-level output power with low loss. The saturated output power of the power amplifier (PA) is 31 dBm at 2.3 GHz. The PA achieves output power of 24.84 dBm with adjacent channel leakage ratio of less than −40.4 dBc for LTE signal with a 10-MHz bandwidth and 7.3-dB PAPR.
Autors: Hyunjin Ahn;Se-Eun Choi;Hyunsik Ryu;Seungjun Baek;Ilku Nam;Ockgoo Lee;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2017, volume: 27, issue:12, pages: 1140 - 1142
Publisher: IEEE
 
» 2017 at a Glance [Editor's Comments]
Abstract:
Presents the introductory editorial for this issue of the publication.
Autors: Mahta Moghaddam;
Appeared in: IEEE Antennas and Propagation Magazine
Publication date: Dec 2017, volume: 59, issue:6, pages: 4 - 4
Publisher: IEEE
 
» 2017 Holiday Gift Guide [Resources]
Abstract:
Autors: Stephen Cass;
Appeared in: IEEE Spectrum
Publication date: Dec 2017, volume: 54, issue:12, pages: 19 - 21
Publisher: IEEE
 
» 2017 International Symposium on Computer Architecture Influential Paper Award
Abstract:
This article discusses the 2017 ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award, which was given to the 2002 ISCA paper, “Drowsy Caches: Simple Techniques for Reducing Leakage Power.”
Autors: David Brooks;
Appeared in: IEEE Micro
Publication date: Dec 2017, volume: 37, issue:6, pages: 90 - 91
Publisher: IEEE
 
» 3-D Dual-Gate Photosensitive Thin-Film Transistor Architectures Based on Amorphous Silicon
Abstract:
In contrast to the conventional planar p-i-n photodiode and a metal-semiconductor–metal photodetector, the 3-D dual-gate photosensitive thin-film transistor (TFT) architectures presented here attain excellent photoresponse characteristics. Operating the device in the subthreshold regime further boosts the photoconductive gain as a result of light-induced decrease in the threshold voltage. This paper presents design considerations along with a performance comparison between 3-D photosensitive TFTs that have - and FIN-shaped channels and conventional TFT with a planar channel. Our paper shows that the -shaped structure tends to have a higher sensitivity while the FIN-shaped counterpart is more responsive with wider dynamic range. For both structures, a measured photoconductive gain of % is obtained with spectral responsivity ranging from near UV to near IR, and the photoresponse time in the range of tens of milliseconds. The 3-D dual-gate photosensitive TFT architecture appears to be very promising for large-area, low-level UV, visible, and IR detection applications.
Autors: Kai Wang;Hai Ou;Jun Chen;Arokia Nathan;Shaozhi Deng;Ningsheng Xu;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2017, volume: 64, issue:12, pages: 4952 - 4958
Publisher: IEEE
 
» 3-D Printed Customizable Inserts for Waveguide Filter Design at X-Band
Abstract:
This letter presents the design of a customizable 3-D printed insert that can be placed into a standard WR-90 waveguide to realize an inline waveguide filter. These 3-D printed inserts have a significantly lower manufacturing cost and turnaround time compared to the conventional solid copper or bronze waveguide. A two-pole X-Band filter insert has been designed to demonstrate this unique approach. A Stratasys Fortus 400mc 3-D printer is used to print the exchangeable waveguide inserts with support material that is then removed using a basic lye solution. A seed layer of nickel is then spray coated on, and used to electroplate the inserts with copper. Measured results are in good agreement with simulation results for the two-pole bandpass filter with less than 1.05-dB insertion loss over X-Band. The weight of these inserts electroplated with copper is only 6.65 g. The ease and flexibility of this approach provides an excellent option for tuning and customizing filter designs with a fast turnaround using 3-D printing manufacturing technology.
Autors: Reena Dahle;Paul Laforge;John Kuhling;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2017, volume: 27, issue:12, pages: 1080 - 1082
Publisher: IEEE
 
» 3-D-Gaze-Based Robotic Grasping Through Mimicking Human Visuomotor Function for People With Motion Impairments
Abstract:
Objective: The goal of this paper is to achieve a novel 3-D-gaze-based human–robot-interaction modality, with which a user with motion impairment can intuitively express what tasks he/she wants the robot to do by directly looking at the object of interest in the real world. Toward this goal, we investigate 1) the technology to accurately sense where a person is looking in real environments and 2) the method to interpret the human gaze and convert it into an effective interaction modality. Looking at a specific object reflects what a person is thinking related to that object, and the gaze location contains essential information for object manipulation. Methods: A novel gaze vector method is developed to accurately estimate the 3-D coordinates of the object being looked at in real environments, and a novel interpretation framework that mimics human visuomotor functions is designed to increase the control capability of gaze in object grasping tasks. Results: High tracking accuracy was achieved using the gaze vector method. Participants successfully controlled a robotic arm for object grasping by directly looking at the target object. Conclusion: Human 3-D gaze can be effectively employed as an intuitive interaction modality for robotic object manipulation. Significance: It is the first time that 3-D gaze is utilized in a real environment to command a robot for a practical application. Three-dimensional gaze tracking is promising as an intuitive alternative for human–robot interaction especially for disabled and elderly people who cannot handle the conventional interaction modalities.
Autors: Songpo Li;Xiaoli Zhang;Jeremy D. Webb;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Dec 2017, volume: 64, issue:12, pages: 2824 - 2835
Publisher: IEEE
 
» 4–20 GHz GaAs True-Time Delay Amplifier MMIC
Abstract:
A wideband amplifier with a fine control of the true-time delay (TTD) has been successfully implemented using a commercial 0.5- GaAs pHEMT monolithic microwave integrated circuit (MMIC) process. The proposed circuit effectively combines switching elements into an artificial transmission line structure in a distributed amplifier to achieve an adjustable TTD which enables time delay control with gain in a wider band than other GaAs-based TTD circuits. The TTD amplifier MMIC achieves a controllable delay of 9 ps, a gain of 9 to 2 dB, and a typical return loss of more than 10 dB from 4 to 20 GHz. The proposed TTD amplifier can be effectively integrated into a multifunction chip based on GaAs semiconductors for wideband active electronically scanned array or phased array systems.
Autors: Dong-Hwan Shin;In-Bok Yom;Dong-Wook Kim;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2017, volume: 27, issue:12, pages: 1119 - 1121
Publisher: IEEE
 
» 40-Gb/s PAM-4 Transmission Over a 40 km Amplifier-Less Link Using a Sub-5V Ge APD
Abstract:
Avalanche photodetectors (APDs) integrated in a silicon platform have the potential to significantly improve the link budget of optical links compared with conventional p-i-n photodetectors, while only requiring CMOS-friendly biasing voltages. We demonstrate an optical receiver based on a 1310nm <5V Germanium APD and a low-power transimpedance amplifier that offers a 5 to 6 dB sensitivity improvement compared with operation in PIN-mode. Sub-FEC transmission using PAM-4 in an amplifier-less link over more than 42km at 40Gb/s and over 10 km at 50 Gb/s is shown with a commercial directly modulated laser as transmitter.
Autors: Jochem Verbist;Joris Lambrecht;Bart Moeneclaey;Joris Van Campenhout;Xin Yin;Johan Bauwelinck;Gunther Roelkens;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2017, volume: 29, issue:24, pages: 2238 - 2241
Publisher: IEEE
 
» 48 GHz High-Performance Ge-on-SOI Photodetector With Zero-Bias 40 Gbps Grown by Selective Epitaxial Growth
Abstract:
High-performance normal-incidence p-i-n Ge photodetectors for 1550 and 1310 nm were grown by selective epitaxial growth on SOI substrate with in situ thermal annealing and surface Si passivation. Bulk leakage current density and surface leakage density as low as 3.4 mA/cm2 and 0.4 μA/cm are achieved under –1 V, respectively. Resonance optical responsivity at 1550 and 1310 nm are 0.27 and 0.59 A/W under zero-bias, respectively. A 3-dB bandwidth as high as 48 GHz is obtained at –3 V. Clear open eye diagrams at 40 Gbps are demonstrated under zero-bias at 1550 nm.
Autors: Zhi Liu;Fan Yang;Wenzhou Wu;Hui Cong;Jun Zheng;Chuanbo Li;Chunlai Xue;Buwen Cheng;Qiming Wang;
Appeared in: Journal of Lightwave Technology
Publication date: Dec 2017, volume: 35, issue:24, pages: 5306 - 5310
Publisher: IEEE
 
» 64-Gb/s SSB-PAM4 Transmission Over 120-km Dispersion-Uncompensated SSMF With Blind Nonlinear Equalization, Adaptive Noise-Whitening Postfilter and MLSD
Abstract:
A novel low-complexity digital signal processing solution is presented to compensate the impairments of limited bandwidth and nonlinearity. It is based on the equalizer, adaptive noise-whitening postfilter, and maximum likelihood sequence detection (MLSD). The system performance loss is induced by higher noise power at the signal band edges after the equalizer can be mitigated by the postfilter and MLSD. Given the above structure, it is possible to enrich the equalizer by providing nonlinear compensation capability. A memory polynomial equalizer (MPE), instead of Volterra equalizer (VE), is applied as the equalizer to compensate the nonlinearity impairments in order to make a tradeoff between complexity and performance. For the adaption of MPE, the blindly adaptive multistep-size decision-directed least-mean-square algorithm is selected. By using a dual-drive Mach–Zehnder and direct detection, 64-Gb/s single-sideband 4-ary pulse amplitude modulation (SSB-PAM4) transmission over 120-km dispersion-uncompensated standard single-mode fiber (SSMF) with 10-dB bandwidth roughly 13.5 GHz is experimentally demonstrated. Given a 20% overhead soft-decision forward-error correction with bit error rate threshold of , the dispersion-uncompensated SSMF transmission distance can be significantly increased from 40 to 120 km with the proposed receiver side solution. The optical signal noise ratio performances for different fiber reach and receiver structure are investigated. Furthermore, we compare the computational complexity of MPE with VE and conclude that MPE can substantially reduce computation complexity with negligible performance loss.
Autors: Zhiquan Wan;Jianqiang Li;Liang Shu;Songnian Fu;Yuting Fan;Feifei Yin;Yue Zhou;Yitang Dai;Kun Xu;
Appeared in: Journal of Lightwave Technology
Publication date: Dec 2017, volume: 35, issue:23, pages: 5193 - 5200
Publisher: IEEE
 
» 65-nm CMOS Front-End Channel for Pixel Readout in the HL-LHC Radiation Environment
Abstract:
A charge preamplifier has been developed in a 65-nm CMOS technology for processing the signals from the inner pixel layers of the CMS detector, in view of the experiment upgrade for the High-Luminosity (HL) Large Hadron Collider (LHC). The circuit is part of a readout channel implementing a time-over-threshold method for the analog-to-digital conversion of the input charge signal. Samples of the circuit have been exposed to high doses of ionizing radiation, up to 500 Mrad(SiO2), from a low-energy proton source and from an X-ray tube. The test results show that the performance degradation, in terms of charge sensitivity, signal shape, and noise, is compatible with operation in the harsh environment of the HL-LHC. Measurement data from the characterization of preamplifiers using different kinds of capacitors in the feedback network help to gain some insight into the damage mechanisms in pMOS transistors irradiated with large ionizing doses. The dependence of performance degradation on the kind of radiation source used in the tests is also discussed.
Autors: Lodovico Ratti;Luigi Gaioni;Massimo Manghisoni;Valerio Re;Elisa Riceputi;Gianluca Traversi;
Appeared in: IEEE Transactions on Nuclear Science
Publication date: Dec 2017, volume: 64, issue:12, pages: 2922 - 2932
Publisher: IEEE
 
» 90 GHz CMOS Phased-Array Transmitter Integrated on LTCC
Abstract:
This paper presents the design of a 90 GHz phased-array transmitter front end on low-temperature co-fired ceramic (LTCC) technology. The monolithic microwave integrated circuit components have been fabricated by the CMOS technology and flip chipped on the LTCC to realize the transmitter front end. The dc and differential hybrid IF signals are provided to the flip-chipped components through the bias and IF lines designed on the LTCC. An patch antenna array has been designed for the transmitter and fabricated on the LTCC. The dc and IF signal pads on the LTCC were soldered to the designed printed circuit board pads for measurements. The measurement results show that by using a receiver horn antenna, the maximum received power at 92 GHz is −37.3 dBm at a communication distance of 1 m. The transmitter is capable of providing ±25° beam steering with respect to boresight and 20° half-power beamwidth at 90 GHz. The total power consumption of the transmitter front end is 656 mW.
Autors: Ali Vahdati;Antti Lamminen;Mikko Varonen;Jussi Säily;Markku Lahti;Kari Kautio;Manu Lahdes;Dristy Parveg;Denizhan Karaca;Kari A. I. Halonen;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2017, volume: 65, issue:12, pages: 6363 - 6371
Publisher: IEEE
 
» 900 V Reverse-Blocking GaN-on-Si MOSHEMTs With a Hybrid Tri-Anode Schottky Drain
Abstract:
In this letter, we present high-performance GaN-on-Si metal-oxide-semiconductor high electron mobility transistors with record reverse-blocking (RB) capability. By replacing the conventional ohmic drain with a hybrid tri-anode Schottky drain, a high reverse breakdown voltage () of −900 V was achieved (at /mm with grounded substrate), along with a small reverse leakage current () of ~20 nA/mm at −750 V. The devices also presented a small turn- on voltage () of 0.58 ± 0.02 V, a small increase in forward voltage () of ~0.8 V, a high ON/OFF ratio over 1010, and a high forward breakdown voltage () of 800 V at 20 nA/mm with grounded substrate. These results demonstrate a new milestone for RB GaN transistors, and open enormous opportunities for integrated GaN power devices.
Autors: Jun Ma;Minghua Zhu;Elison Matioli;
Appeared in: IEEE Electron Device Letters
Publication date: Dec 2017, volume: 38, issue:12, pages: 1704 - 1707
Publisher: IEEE
 
» In Situ Observation of Metal Properties in a Piezoresistive Pressure Sensor
Abstract:
Relaxation phenomena in metal interconnects are a potential source of drift in piezoresistive pressure sensors. Since the properties of a metal film are influenced by its fabrication process, it is of interest to study such phenomena in an environment that resembles a production device. For this purpose, a piezoresistive pressure sensor has been modified for characterization of thin film metallization. Extra metal has been placed on the passivation layer over the piezoresistors such that the strain in the metal can be controlled isothermally by applying a test pressure as well as by temperature. We show that the sensor output signal contains information on the stress development in the metal film. By limiting the design modification to one metal mask only, we have achieved a cost effective approach for characterization of metal properties with test structures that can be processed together with functional devices. [2017-0074]
Autors: Åsmund Sandvand;Einar Halvorsen;Henrik Jakobsen;
Appeared in: Journal of Microelectromechanical Systems
Publication date: Dec 2017, volume: 26, issue:6, pages: 1381 - 1388
Publisher: IEEE
 
» In-Situ Monitoring the Degradation of LEDs En Route the Visible Light Communication System
Abstract:
White light-emitting diodes (LEDs) offer the opportunity to realize energy efficient illumination and high-speed free-space visible light communication (VLC) simultaneously. The decrease of the optical power (OP) was usually used to characterize the degradation of LEDs, but the degradation does not always and only refers to a decrease in OP. This paper proposes using the characteristics parameters of VLC performances as in-situ indicators of the degradation of the LED light source itself. LED devices being intentionally stressed for 168 h at 120 °C and 85% relative humidity and 350 mA are used for demonstration. Stressing generates new defects in LED chips, which is accompanied by the decrease of frequency-response bandwidth and bit-error rate values of LEDs at the rated voltages. Compared with low-frequency light intensity noise characterization methods, the VLC system is something like to measure a dimming optical noise, featured by free-space measurement and compatibility with the existing illumination and wireless communication system.
Autors: Lilin Liu;Xiangying Zhang;Lu Li;Dongdong Teng;Gang Wang;
Appeared in: IEEE Transactions on Device and Materials Reliability
Publication date: Dec 2017, volume: 17, issue:4, pages: 722 - 726
Publisher: IEEE
 
» FeSSD: A Fast Encrypted SSD Employing On-Chip Access-Control Memory
Abstract:
Cryptography is one of the most popular methods for protecting data stored in storage devices such as solid-state drives (SSDs). To maintain integrity of data, one of the popular techniques is that all incoming data are encrypted before they are stored, however, in this technique, the encryption overhead is non-negligible and it can increase I/O service time. In order to mitigate the negative performance impact caused by the data encryption, a write buffer can be used to hide the long latency by encryption. Using the write buffer, incoming unencrypted data can be immediately returned as soon as they are written in the buffer. They will get encrypted and synchronized with flash memory. However, if the write buffer itself is not encrypted, unencrypted secret data might leak through this insecure write buffer. On the other hand, if the entire write buffer is fully encrypted, it incurs significant performance overhead. To address this problem, we propose an on-chip access control memory (ACM) and presents a fast encrypted SSD, called FeSSD that implements a secure write buffering mechanism using the ACM. The ACM does not require a memory-level full encryption mechanism, thus not only solving the unencrypted data leaking problem, but also offering relatively fast I/O service. Our simulation results show that the I/O response time of FeSSD can be improved by up to 56 percent over a baseline where encrypted data are stored in the normal write buffer.
Autors: Junghee Lee;Kalidas Ganesh;Hyuk-Jun Lee;Youngjae Kim;
Appeared in: Computer Architecture Letters
Publication date: Dec 2017, volume: 16, issue:2, pages: 115 - 118
Publisher: IEEE
 
» A $200~mu text{m}$ by $100~mu text{m}$ Smart Submersible System With an Average Current Consumption of 1.3nA and a Compatible Voltage Converter
Abstract:
In this paper, we present a novel microscale “Smart Dust” type system designed to operate in aqueous solutions, with a volume of 35 , called a lablet. The lablet contains a 20Hz low-power clock generator, a sensor, electric actuators, and a simple finite state machine to implement a predefined response to the sensor input. It is designed to be rechargeable and to communicate via local contacts through aqueous solution either between lablets or with a docking station chip. The system operates with supply voltages ranging from 0.3 to 1.8V and is thus suitable to be supplied from a capacitor with decreasing voltage. An input rectifier allows powering the lablet independent of polarity. The average current consumption of the system was measured to be 1.3nA when supplied from a capacitor with an initial voltage of 1.8V. The small system scale allows the investigation of “pourable electronics”, a concept where large quantities of microsystems are deployed within a chemical solution to perform a predefined task. Several lablets have been designed and fabricated in a standard 180nm CMOS process and the electrical functionality has been verified by contacting the lablet electrodes with multiple probe needles. In order to use low voltage energy sources to supply the lablet, a voltage up-converter has been designed which is small enough to fit on the lablet.
Autors: Dominic A. Funke;Philipp Hillger;Jürgen Oehm;Pierre Mayr;Lukas Straczek;Nils Pohl;John S. McCaskill;
Appeared in: IEEE Transactions on Circuits and Systems I: Regular Papers
Publication date: Dec 2017, volume: 64, issue:12, pages: 3013 - 3024
Publisher: IEEE
 
» A $D$ -Band Low-Power Gain-Boosted Up-Conversion Mixer With Low LO Power in 40-nm CMOS Technology
Abstract:
This letter presents a -band low-power gain-boosted up-conversion mixer using the 40-nm comple- mentary metal–oxide–semiconductor technology. The proposed up-conversion mixer adopted gain-boost technique to improve conversion gain with a low local oscillator (LO) power. The resistive-feedback inverter was employed for wideband matching at intermediate-frequency ports. Broadband Marchand baluns were used to transform a single-ended signal to a differential signal at the RF and LO ports for measurement. The proposed up-conversion mixer demonstrated a measured conversion gain of −5 dB ± 1 dB at frequencies from 105 to 135 GHz with an ultralow LO power of −10 dBm. The average LO-RF isolation was −35 dB. The measured input P1dB compression point was −7.5 dBm. This core chip occupies and the total power consumption is 9 mW from a 1-V supply voltage.
Autors: Chae Jun Lee;Jin-Seob Kang;Chul Soon Park;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2017, volume: 27, issue:12, pages: 1113 - 1115
Publisher: IEEE
 
» A $K$ -Band High-Efficiency VCO Using Current Reused Technique
Abstract:
In this letter, we present a high-efficiency CMOS voltage control oscillator (VCO) at K-Band. In order to achieve high efficiency, we adopt center-tapped transformer and current reused technique to integrate cross couple pair and buffer amplifier. In addition, we put buffer amplifier gate bias at class AB to enhance efficiency. VCO tuning range is from 22.35 to 25.31 GHz. Across the VCO frequency range, peak output power and best efficiency are 4.37 dBm and 10.93%, respectively. Phase noise is better than −101 dBc/Hz at 1 MHz offset at all tuning range. Total dc power consumption is only 25 mW for 1.8-V supplied voltage. To our best knowledge, this VCO has excellent dc to RF efficiency at K-band.
Autors: Yu-Teng Chang;Hsin-Chia Lu;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2017, volume: 27, issue:12, pages: 1134 - 1136
Publisher: IEEE
 
» A 0.4-to-1 V Voltage Scalable $Delta Sigma $ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS
Abstract:
This brief presents a two-step hybrid integrator (TSHI) that can operate at a wide supply voltage range, which is demonstrated with a third-order analog-to-digital converter (ADC). The proposed TSHI consists of a zero-crossing-detector (ZCD)-based integrator and an inverter-based integrator. In the coarse-integration step, the ZCD-based integrator performs a fast integration without concern for overshoot or detection delay issues. In the fine-integration step, the inverter-based integrator performs the residual integration with high accuracy. Hence, the TSHI provides fast and accurate integration process. In addition, the TSHI supports trade-off between voltage-scalable bandwidth and power consumption for an energy efficient operation of Internet-of-Things sensor nodes, owing to the scalable operation of the ZCD and inverter. The proposed ADC is fabricated in a 65-nm LP CMOS process, and the active area is 0.38 mm2. The fabricated ADC operates at supply voltages from 0.4 to 1 V. Depending on the supply voltage and sampling frequency, the power consumption and bandwidth of the ADC can be scaled from 12.7 to and from 7.5 to 400 kHz, respectively. The ADC maintains an SNDR higher than 60 dB within the operating supply range.
Autors: Jun-Eun Park;Young-Ha Hwang;Deog-Kyoon Jeong;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2017, volume: 64, issue:12, pages: 1417 - 1421
Publisher: IEEE
 
» A 0.5erms Temporal Noise CMOS Image Sensor With Gm-Cell-Based Pixel and Period-Controlled Variable Conversion Gain
Abstract:
A deep subelectron temporal noise CMOS image sensor (CIS) with a Gm-cell based pixel and a correlated-double charge-domain sampling technique has been developed for photon-starved imaging applications. With the proposed technique, the CIS, which is implemented in a standard 0.18- CIS process, features pixel-level amplification and achieves an input-referred noise of 0.5 erms with a correlated double sampling period of and a row read-out time of . The proposed structure also realizes a variable conversion gain (CG) with a period-controlled method. This enables the read-out path CG and the noise-equivalent number of electrons to be programmable according to the application without any change in hardware. The experiments show that the measured CG can be tuned from /e- to 1.6 mV/e- with a charging period from 100 ns to . The measured characteristics of the prototype CIS are in a good agreement with expectations, demonstrating the effectiveness of the proposed techniques.
Autors: Xiaoliang Ge;Albert J. P. Theuwissen;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2017, volume: 64, issue:12, pages: 5019 - 5026
Publisher: IEEE
 
» A 1.1- $mu text{m}$ 33-Mpixel 240-fps 3-D-Stacked CMOS Image Sensor With Three-Stage Cyclic-Cyclic-SAR Analog-to-Digital Converters
Abstract:
In this paper, a 1.1--pitch 33-Mpixel 240-fps backside-illuminated 3-D-stacked CMOS image sensor with three-stage cyclic-cyclic-successive-approximation-register (SAR) analog-to-digital converters (ADCs) is developed. The narrow-pitch interconnection technology that connects the pixels and arrayed ADCs inside the pixel area is described. The 3-D-stacked architecture, constructed using the interconnection technology, makes it possible to place a correlated-double-sampling/ADC array underneath the pixel area. Furthermore, the pipelined and parallel operation of the three-stage cyclic-cyclic-SAR ADC architecture effectively reduces the conversion time period and power consumption and achieves 12-b precision within one horizontal scan time of . As a result, the interconnection technology and ADC architecture achieved a high frame rate of 240 fps in 33 Mpixels. Random noise of 3.6 and low power consumption of 3.0 W were attained at an extremely high pixel rate of 7.96 Gpixel/s. A good figure of merit is achieved compared with recently developed image sensors.
Autors: Toshiki Arai;Toshio Yasue;Kazuya Kitamura;Hiroshi Shimamoto;Tomohiko Kosugi;Sung-Wook Jun;Satoshi Aoyama;Ming-Chieh Hsu;Yuichiro Yamashita;Hirofumi Sumi;Shoji Kawahito;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2017, volume: 64, issue:12, pages: 4992 - 5000
Publisher: IEEE
 
» A 1.15-ps Bin Size and 3.5-ps Single-Shot Precision Time-to-Digital Converter With On-Board Offset Correction in an FPGA
Abstract:
This paper presents the implementation of a high-resolution time-to-digital converter (TDC), which is adapted to varying environmental conditions. The TDC is implemented in field-programmable gate arrays (FPGA), using carry chains to achieve fine time measurement. Multiple carry chains are integrated in a single TDC channel for resolution enhancement. The TDC performance would suffer greatly without temperature compensation due to its sensitivity to the operating temperature. In order to improve the TDC adaptability, we analyzed the temperature-dependent delay variation function, and designed a powerful offset canceler to ensure stable performance of our TDC over a wide temperature range. The offset canceler can effectively correct the delay offset over temperature for the carry chain as well as for the signal transmission path. The TDC channels are tested to be fully functional with the operating temperature continuously varying from −20 °C to 60 °C. The averaged TDC bin size is 1.15 ps, and the single-shot precision is 3.5 ps. The duplications of the TDCs in three FPGA chips show good performance reproducibility according to the tests in a temperature chamber.
Autors: X. Qin;L. Wang;D. Liu;Y. Zhao;X. Rong;J. Du;
Appeared in: IEEE Transactions on Nuclear Science
Publication date: Dec 2017, volume: 64, issue:12, pages: 2951 - 2957
Publisher: IEEE
 
» A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR
Abstract:
A dc-20-GHz multiple-return-to-zero digital-to-analog converter (DAC) is proposed for direct radio frequency synthesis. To minimize frequency-dependent amplitude and phase errors in the output summing node, which can dominate linearity performance at GHz and mm-wave frequencies, a vertically stacked tree (VST) and feed-forward (FF) path are proposed. While the VST minimizes variation in frequency response among the MSB cells, the FF path improves matching between the MSBs and LSBs, providing up to 21-dB improvement in simulated spurious-free dynamic range (SFDR) at 20 GHz. To account for additional errors introduced by process variation, the DAC utilizes per-cell calibration of both amplitude and timing. The DAC is implemented in a 0.13- SiGe process with an area of 6.25 mm2 and consumes 1.91 W. After amplitude and timing calibration, >48-dB SFDR and lesser than −46 dBc intermodulation distortion are achieved from dc to 20 GHz.
Autors: Lucas Duncan;Brian Dupaix;Jamin J. McCue;Brandon Mathieu;Matthew LaRue;Vipul J. Patel;Mesfin Teshome;Myung-Jun Choe;Waleed Khalil;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3262 - 3275
Publisher: IEEE
 
» A 10-Gb/s Optical Receiver With Sub-Microampere Input-Referred Noise
Abstract:
High-speed optical receivers realized in low-cost technology often suffer from unfavorable performance, dictated by the transimpedance limit, the key design constraint of shunt-shunt feedback transimpedance amplifier (TIA). In this letter, we propose a novel TIA architecture to overcome the transimpedance limit, achieving both low noise and high gain that are not realizable in a conventional topology. A 10-Gb/s optical receiver with sub-microampere input-referred noise current is implemented in a mature 0.18- CMOS technology. Wire-bonded with a commercial III–V p-i-n photodiode, the receiver demonstrates the state-of-the-art input-referred noise current of 0.97 Arms and a total transimpedance gain of 68.3 dB while consuming 45 mA from 1.8-V power supply. Finally, the proposed architecture is applicable to 10 Gb/s beyond to realize low-noise high-gain optical receivers.
Autors: Dan Li;Ming Liu;Li Geng;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2017, volume: 29, issue:24, pages: 2268 - 2271
Publisher: IEEE
 
» A 118-mW Pulse-Based Radar SoC in 55-nm CMOS for Non-Contact Human Vital Signs Detection
Abstract:
We report a direct-RF pulse-based radar System on Chip (SoC) with applications in vital signs monitoring and occupancy detection. The transmitter complies with FCC, ETSI, and KCC regulatory masks with −10 dB bandwidths of 1.4 and 1.5 GHz centered at 7.29 and 8.748 GHz. The receiver samples the reflected signal at 23.328 GS/s, covering a 9.9-m consecutive range. The measured front-end noise figure is 6.3 dB with 14.7-dB gain at 7.29 GHz. Chest movements from breathing and heartbeats in a human subject were detected at 9 and 5 m, respectively. All required power management and clock functions are integrated on-chip. The SoC was implemented in 55-nm CMOS. In active mode, the system consumes 118 mW from a 1.8-V power supply.
Autors: Nikolaj Andersen;Kristian Granhaug;Jørgen Andreas Michaelsen;Sumit Bagga;Håkon A. Hjortland;Mats Risopatron Knutsen;Tor Sverre Lande;Dag T. Wisland;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3421 - 3433
Publisher: IEEE
 
» A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
Abstract:
A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push–pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs.
Autors: Siddharth Devarajan;Larry Singer;Dan Kelly;Tao Pan;Jose Silva;Janet Brunsilius;Daniel Rey-Losada;Frank Murden;Carroll Speir;Jeffery Bray;Eric Otte;Nevena Rakuljic;Phil Brown;Todd Weigandt;Qicheng Yu;Donald Paterson;Corey Petersen;Jeffrey Gealow;Gabri
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3204 - 3218
Publisher: IEEE
 
» A 128-Channel FPGA-Based Real-Time Spike-Sorting Bidirectional Closed-Loop Neural Interface System
Abstract:
A multichannel neural interface system is an important tool for various types of neuroscientific studies. For the electrical interface with a biological system, high-precision high-speed data recording and various types of stimulation capability are required. In addition, real-time signal processing is an important feature in the implementation of a real-time closed-loop system without unwanted substantial delay for feedback stimulation. Online spike sorting, the process of assigning neural spikes to an identified group of neurons or clusters, is a necessary step to make a closed-loop path in real time, but massive memory-space requirements commonly limit hardware implementations. Here, we present a 128-channel field-programmable gate array (FPGA)-based real-time closed-loop bidirectional neural interface system. The system supports 128 channels for simultaneous signal recording and eight selectable channels for stimulation. A modular 64-channel analog front-end (AFE) provides scalability and a parameterized specification of the AFE supports the recording of various electrophysiological signal types with 1.59 ± 0.76 root-mean-square noise. The stimulator supports both voltage-controlled and current-controlled arbitrarily shaped waveforms with the programmable amplitude and duration of pulse. An empirical algorithm for online real-time spike sorting is implemented in an FPGA. The spike-sorting is performed by template matching, and templates are created by an online real-time unsupervised learning process. A memory saving technique, called dynamic cache organizing, is proposed to reduce the memory requirement down to 6 kbit per channel and modular implementation improves the scalability for further extensions.
Autors: Jongkil Park;Gookhwa Kim;Sang-Don Jung;
Appeared in: IEEE Transactions on Neural Systems and Rehabilitation Engineering
Publication date: Dec 2017, volume: 25, issue:12, pages: 2227 - 2238
Publisher: IEEE
 
» A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
Abstract:
A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137- and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a frequency multiplication ratio of 207.0019231 [digitally controlled oscillator (DCO) frequency is 50 kHz away from an integer multiple of the 26-MHz reference clock], a −78.6-dBc fractional spur is achieved for an output clock that runs at half of the DCO frequency. Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog-to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs. This design meets the performance requirement of the 256-QAM MIMO LTE standard in 5-GHz ISM band and also the 5G cellular 64-QAM standard in 28-GHz band. This work, implemented in a 14-nm fin-shaped field effect transistor (FinFET) CMOS process, is integrated to a cellular RF integrated circuit supporting advanced carrier aggregation operation. This PLL draws 13.4 mW and occupies 0.257 mm2.
Autors: Chih-Wei Yao;Ronghua Ni;Chung Lau;Wanghua Wu;Kunal Godbole;Yongrong Zuo;Sangsoo Ko;Nam-Seog Kim;Sangwook Han;Ikkyun Jo;Joonhee Lee;Juyoung Han;Daehyeon Kwon;Chulho Kim;Shinwoong Kim;Sang Won Son;Thomas Byunghak Cho;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3446 - 3457
Publisher: IEEE
 
» A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path
Abstract:
In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125 °C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore’s gap between the high-performance logic and the embedded memory.
Autors: E. Ray Hsieh;Yen Chen Kuo;Chih-Hung Cheng;Jing Ling Kuo;Meng-Ru Jiang;Jian-Li Lin;Hung-Wen Chen;Steve S. Chung;Chuan-Hsi Liu;Tse Pu Chen;Shih An Huang;Tai-Ju Chen;Osbert Cheng;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2017, volume: 64, issue:12, pages: 4910 - 4918
Publisher: IEEE
 
» A 19 nV/ $surd$ Hz Noise 2- $mu text{V}$ Offset 75- $mu text{A}$ Capacitive-Gain Amplifier With Switched-Capacitor ADC Driving Capability
Abstract:
This paper describes a capacitive-gain amplifier (CGA) with common-mode (CM) sampling (CMS) and switched-capacitor driving capability. The CMS CGA defines the amplifier CM voltage in a single auto-zero phase that significantly reduces the CM settling time. A pre-charge technique and dynamic filtering are used to allow the CGA to drive a switched-cap analog-to-digital converter (ADC) directly that relaxes the speed requirement on CGA and reduces folded noise aliases due to ADC sampling. As a result, it achieves 19-nV/Hz noise density while dissipating 75 . The 5 ppm/full-scale-range integral nonlinearity is achieved with programmable gain range from 1 to 128 with 2.7 to 3.6 V supply. It has 2 typical offset and 0.81 ppm/°C max gain error drift. The CGA was implemented in a 0.18- CMOS 1.8/3.3 V ultra low leakage technology and occupies only 0.53 mm2 die area.
Autors: Hanqing Wang;Gerard Mora-Puchalt;Colin Lyden;Roberto Maurino;Christian Birk;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3194 - 3203
Publisher: IEEE
 
» A 190-GHz High-Gain, 3-dBm OP1dB Low DC-Power Amplifier in 250-nm InP HBT
Abstract:
We report a 190-GHz amplifier designed into a 250-nm InP HBT technology. The four-stage amplifier at 76-mW dc power demonstrates 25-dB gain and 24-GHz 3-dB bandwidth. At 190-GHz operation, the saturated output power is 9.7-mW with 9.4% PAE and 16.4-dB large-signal gain. The 1-dB gain compression power OP1dB is 3-dBm. Biased at 97-mW using higher HBT collector voltage, the amplifier demonstrates 22.4-dB gain and 26-GHz 3-dB bandwidth. At 190-GHz operation, increases to 12.7-mW with 9.5% PAE and 19.2-dB large-signal gain. The OP1dB is also 3 dBm. Very similar OP1dB, , and PAE large-signal characteristics were observed at 185- and 195-GHz operation. This letter represents world-class efficiency and record 1.59-W/mm power density for an InP HBT amplifier operating at G-band, and it competes equally well with the state-of-the-art results demonstrated in advanced InP HEMT, SiGe HBT, and CMOS technologies.
Autors: Zach Griffith;Miguel Urteaga;Petra Rowell;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2017, volume: 27, issue:12, pages: 1128 - 1130
Publisher: IEEE
 
» A 2–22 GHz CMOS Distributed Power Amplifier With Combined Artificial Transmission Lines
Abstract:
This letter presents a novel compact distributed power amplifier (DPA) implemented in a 0.18- CMOS technology. Two three-stage DAs are combined with their input artificial transmission lines (ATLs) shared to work as a preamplifier for broadband impedance matching and gain improvement, while two four-stage DAs are combined with their output ATLs shared to work as a medium-power amplifier for high output power in a wide frequency band. Measurement results show that the DPA provides 11.9-dB average associated gain from 1 to 23.8 GHz. The output power at 1-dB output compression point ( is more than 8.9 dBm over the frequency of 2–22 GHz, and the peak power-added efficiency is 10% with the of 14.5 dBm.
Autors: Ying Zhang;Kaixue Ma;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2017, volume: 27, issue:12, pages: 1122 - 1124
Publisher: IEEE
 
» A 2-D Nonlinear Chirp Scaling Algorithm for High Squint GEO SAR Imaging Based on Optimal Azimuth Polynomial Compensation
Abstract:
GEO SAR can achieve better revisit time and observation performances when using high squint mode. However, high squint mode also causes huge range walk and severe range-azimuth coupling problems as well as severe 2-D spatial variance of the focusing parameters and range cell migration (RCM), which restrict the available scene size and increase the difficulty of GEO SAR imaging. To achieve high squint mode GEO SAR imaging, the effects of squint mode on imaging processing—especially the azimuth-variant RCM—are first analyzed in detail, and the relationship between the azimuth-variant RCM and the azimuth-variant focus parameters is discussed. Then, in this paper, a 2-D nonlinear chirp scaling algorithm (2-D NCSA) based on optimal azimuth polynomial compensation is proposed to realize high squint GEO SAR imaging. In the proposed algorithm, the optimal azimuth polynomial compensation which consists of a time-domain compensation and a frequency compensation removes the range walk, weakens the azimuth-variant RCM, and simplifies the imaging processing, while the 2-D NCSA which consists of a range NCSA and a higher order azimuth NCSA solves the 2-D spatial variance of focusing parameters and achieves high squint GEO SAR imaging. Computer simulations for different orbital positions validate the effectiveness of the proposed algorithm under high squint conditions.
Autors: Tianyi Zhang;Zegang Ding;Weiming Tian;Tao Zeng;Wei Yin;
Appeared in: IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
Publication date: Dec 2017, volume: 10, issue:12, pages: 5724 - 5735
Publisher: IEEE
 
» A 2.4-GHz, Hybrid 10-Mb/s BPSK Backscatter and 1-Mb/s FSK Bluetooth TX With Hardware Reuse
Abstract:
This letter presents a hybrid architecture for wireless transmitters that reuses the same hardware and antenna to selectively operate in either backscatter or conventional modes, with a minimum of added complexity. A single FET stage is used as both a Class-C power amplifier for a conventional 2.4-GHz, 1-Mb/s frequency shift keying Bluetooth low energy (BLE) transmitter with peak efficiency %, as well as a 10-Mb/s BPSK modulator in an ultralow power backscatter mode. A transmitter energy consumption of 81 nJ/b at an output power level of +14 dBm is achieved in the 1-Mb/s conventional mode, while only 32 pJ/b is required in the 10-Mb/s BPSK backscatter mode. It is shown that the data rate of the backscatter mode can be decoupled from the conventional mode, such that the backscatter link can operate at ten times the rate of the conventional link, while achieving over three orders of magnitude power savings. This approach is equally applicable to other communication standards, such as Wi-Fi (IEEE 802.11b), Zigbee (IEEE 802.15.4), and so on.
Autors: Matthew S. Reynolds;
Appeared in: IEEE Microwave and Wireless Components Letters
Publication date: Dec 2017, volume: 27, issue:12, pages: 1155 - 1157
Publisher: IEEE
 
» A 20-nW 0.25-V Inverter-Based Asynchronous Delta–Sigma Modulator in 130-nm Digital CMOS Process
Abstract:
This paper presents a new inverter-based architecture that implements an asynchronous delta–sigma modulator. Different from the classical architecture, it features an input transconductor that promotes a differential and high input impedance that makes it easier to interface with sensors and other front ends. Furthermore, an inverter-based relaxation oscillator accomplishes the required hysteresis through a charge redistribution process, which exhibits lower time delay than hysteretic comparators, besides saving power from quiescent biasing. The circuit has been implemented in 130-nm CMOS digital process using halo-implanted transistors. In addition, transistors are biased in weak inversion and are implemented using distributed layout to reduce power consumption besides mitigating halo-implants undesired effects. Supplied with 0.25 V, the proposed architecture consumes 20 nW with just −55 dB of third harmonic distortion, making it suitable for wearable biomedical applications where energy consumption, low bandwidth, and moderate resolution are required.
Autors: Gustavo Della Colletta;Luís H. C. Ferreira;Sameer R. Sonkusale;Giseli V. Rocha;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2017, volume: 25, issue:12, pages: 3455 - 3463
Publisher: IEEE
 
» A 21st Century Cyber-Physical Systems Education
Abstract:
The rapid rate of change in the computing and engineering domains has our educational institutions on high alert. The authors explore how best to prepare graduates for a world in which cyber-physical systems are increasingly ubiquitous.
Autors: John A. Stankovic;James W. Sturges;Jon Eisenberg;
Appeared in: Computer
Publication date: Dec 2017, volume: 50, issue:12, pages: 82 - 85
Publisher: IEEE
 
» A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS
Abstract:
This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) to achieve data rates from 22.5 to 32 Gb/s across a channel with Nyquist loss ranging from 10.1 to 14.8 dB. The referenceless CDR includes a proposed frequency acquisition scheme that consists of two parts: frequency detection and frequency correction. Frequency detection is achieved by examining rising and falling data waveforms to detect discrepancies between the data rate and the locally recovered clock frequency. Frequency correction uses digitally adjustable asymmetry of the proposed adjustable baud-rate phase detector to correct any frequency error. The receiver is implemented in the TSMC 28-nm CMOS process with an analog front end consisting of a CTLE, sampling comparators, a digitally controlled oscillator, and a digital back end consisting of synthesized digital CDR logic. The open-loop frequency detector range is measured to be 39%. The closed-loop CDR capture range is measured to be 34%, limited by test equipment. The proposed frequency acquisition scheme improves the measured CDR capture range by up to . At 32 Gb/s, the entire receiver consumes 102.04 mW, achieving energy consumption below 3.19 pJ/b.
Autors: Wahid Rahman;Danny Yoo;Joshua Liang;Ali Sheikholeslami;Hirotaka Tamura;Takayuki Shibasaki;Hisakatsu Yamaguchi;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3517 - 3531
Publisher: IEEE
 
» A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and $G_{m}$ -Regulated Resistive-Feedback Driver
Abstract:
We presents an energy-efficient PAM-4 transmitter that provides a controlled output impedance, scalable output voltage swing, and fractionally spaced feed-forward equalization (FFE). By using a resistive-feedback output driver, the proposed PAM-4 transmitter can reduce the power dissipation in the pre-driver stages compared with conventional transmitters. It also offers a more straightforward implementation of a 3-tap FFE owing to the simple current-summing structure of the pre-driver. In addition, the output impedance of the proposed output driver is controlled by regulating the of the driver cell, which results in good signal integrity for high-speed operation without the use of peaking inductors. A prototype chip is fabricated in 28-nm CMOS technology and occupies an active area of 0.048 mm2. It achieves a data rate of 28 Gb/s, exhibiting the state-of-the-art energy efficiency of 1.59 pJ/b for the differential output swing of 207 mV.
Autors: Haram Ju;Moon-Chul Choi;Gyu-Seob Jeong;Woorham Bae;Deog-Kyoon Jeong;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2017, volume: 64, issue:12, pages: 1377 - 1381
Publisher: IEEE
 
» A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications
Abstract:
This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (<0.6° rms error) across a ±50° steering range without requiring calibration. A maximum saturated effective isotropic radiated power of 54 dBm is measured in the broadside direction for each polarization. Tapering control without requiring calibration achieves up to 20-dB sidelobe rejection without affecting the main lobe direction.
Autors: Bodhisatwa Sadhu;Yahya Tousi;Joakim Hallin;Stefan Sahl;Scott K. Reynolds;Örjan Renström;Kristoffer Sjögren;Olov Haapalahti;Nadav Mazor;Bo Bokinge;Gustaf Weibull;Håkan Bengtsson;Anders Carlinger;Eric Westesson;Jan-Erik Thil
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3373 - 3391
Publisher: IEEE
 
» A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist
Abstract:
The implementation of the six-transistor (6T) static random access memory cell in deep submicrometer region has become difficult due to the compromise between area, power, and performance, with local and global variations only exacerbating the problem further. To impede the read–write conflict of the 6T cell, the seven-transistor (7T) cell with a noise-margin-free read operation has previously been proposed. But it severely lags in terms of its write ability at lower voltages due to its single-ended write operation. Its single-ended read operation also degrades severely in performance when operating in subthreshold (ST) region. To combat these problems, we propose a 7T cell which operates in the ST region down to 0.4 V with improved dynamic write ability. The novel topology also helps reduce power consumption by achieving a lower data retention voltage point. A read assist has been proposed to greatly enhance the performance of the single-ended read operation in ST region. Large improvements in various performance metrics of the proposed cell have been attained while simultaneously achieving a low area of per bit cell on the 32-nm technology node.
Autors: Shourya Gupta;Kirti Gupta;Neeta Pandey;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2017, volume: 25, issue:12, pages: 3473 - 3483
Publisher: IEEE
 
» A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET
Abstract:
This brief presents a 4-GS/s single channel folding flash analog-to-digital converter (ADC) designed to be time-interleaved for wireline receivers in 16-nm FinFET CMOS. The resolution of the ADC is scalable to enable power savings depending on link modulation format (2 PAM/4 PAM) and link loss. A 1-bit folding stage determines the MSB, while the LSBs are determined by a 5-bit full flash where each comparator can be individually enabled/disabled. At 6-bit resolution, the ADC including a variable gain amplifier achieves an SNDR of 30.7 dB and an SFDR of 40.6 dB at Nyquist frequency while consuming 34.4 mW from a 0.9-V supply, yielding an FOM of 303 fJ/conv-step. At lower resolutions of 5, 4, and 3 bits, the FOM remains low at 295, 320, and 399 fJ/conv-step, respectively, at Nyquist frequency.
Autors: Luke Wang;Marc-Andre LaCroix;Anthony Chan Carusone;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2017, volume: 64, issue:12, pages: 1367 - 1371
Publisher: IEEE
 
» A 40-Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45-nm SOI CMOS
Abstract:
The next generations of large-scale data-centers and supercomputers demand optical interconnects to migrate to 400G and beyond. Microring modulators in silicon-photonics VLSI chips are promising devices to meet this demand due to their energy efficiency and compatibility with dense wavelength division multiplexed chip-to-chip optical I/O. Higher order pulse amplitude modulation (PAM) schemes can be exploited to mitigate their fundamental energy–bandwidth tradeoff at the system level for high data rates. In this paper, we propose an optical digital-to-analog converter based on a segmented microring resonator, capable of operating at 20 GS/s with improved linearity over conventional optical multi-level generators that can be used in a variety of applications such as optical arbitrary waveform generators and PAM transmitters. Using this technique, we demonstrate a PAM-4 transmitter that directly converts the digital data into optical levels in a commercially available 45-nm SOI CMOS process. We achieved 40-Gb/s PAM-4 transmission at 42-fJ/b modulator and driver energies, and 685-fJ/b total transmitter energy efficiency with an area bandwidth density of 0.67 Tb/s/mm2. The transmitter incorporates a thermal tuning feedback loop to address the thermal and process variations of microrings’ resonance wavelength. This scheme is suitable for system-on-chip applications with a large number of I/O links, such as switches and general-purpose and specialized processors in large-scale computing and storage systems.
Autors: Sajjad Moazeni;Sen Lin;Mark Wade;Luca Alloatti;Rajeev J. Ram;Miloš Popović;Vladimir Stojanović;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3503 - 3516
Publisher: IEEE
 
» A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET
Abstract:
A 40–56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design implements direct feedback of the first post-cursor (h1) DFE tap to reduce the number of slicers. The h1 feedback signals are directly tapped from the master latch output of the StrongArm-based slicers. A CMOS amplifier with delayed pre-charge release is used to boost and pre-condition the h1 feedback signals before being applied to current-mode logic tap cell for optimum DFE summer settling time. The receiver achieves less than 1E-12 PRBS31 bit error rate (BER) over a channel with 10-dB loss at 14-GHz consuming 230 mW. Fully adapted by off-chip software, the receiver performance demonstrates the effectiveness of direct h1 loop and the need for higher DFE taps to achieve a required BER over channels with reflections. Receiver performance over higher loss channels up to 23 dB and/or under emulated cross-talk noise injection cases are also presented.
Autors: Jay Im;Dave Freitas;Arianne Bantug Roldan;Ronan Casey;Stanley Chen;Chuen-Huei Adam Chou;Tim Cronin;Kevin Geary;Scott McLeod;Lei Zhou;Ian Zhuang;Jaeduk Han;Sen Lin;Parag Upadhyaya;Geoff Zhang;Yohan Frans;Ken Chang;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3486 - 3502
Publisher: IEEE
 
» A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS
Abstract:
We present a single-channel 10-b 400-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) embodying a proposed 2-b/step conversion scheme with single reference voltage for the IEEE 802.11ac. By means of the said scheme, the proposed ADC requires only three capacitor arrays instead of at least four capacitor arrays in other capacitor digital-to-analog converter-based 2-b/step SAR ADCs. The proposed ADC features a small input capacitance loading, thereby alleviating the driving requirement of the power-hungry input buffer in the IEEE 802.11ac system; and features a symmetrical architecture with highly matched interconnections. In addition, the proposed ADC embodies a proposed high-speed dynamic comparator with kickback noise cancelation and high-speed successive approximation (SA) control logic for high conversion rate and resolution. The proposed ADC prototype fabricated in 65-nm CMOS process achieves signal-to-noise-and-distortion-ratio >52 dB across 200-MHz Nyquist bandwidth, while dissipating 5.61-mW power. The ADC prototype, when benchmarked with state-of-the-art 2-b/step SAR ADCs, features a highly competitive figure-of-merit, i.e., 43 fJ/conv.step.
Autors: Qing Liu;Wei Shu;Joseph S. Chang;
Appeared in: IEEE Transactions on Very Large Scale Integration Systems
Publication date: Dec 2017, volume: 25, issue:12, pages: 3444 - 3454
Publisher: IEEE
 
» A 4th-Order Continuous-Time Delta-Sigma Modulator Using 6-bit Double Noise-Shaped Quantizer
Abstract:
This paper presents a continuous-time delta-sigma modulator using a double noise-shaped quantizer (DNSQ), which not only provides 2nd-order noise shaping but also generates a 6-bit quantization in the modulator. The proposed DNSQ efficiently extracts the quantization error in the time domain from a noise-shaped integrating quantizer (NSIQ), and directly applies it to a gated ring oscillator-based quantizer, hence achieving a 2nd order of noise shaping on its own. By incorporating the DNSQ, the modulator can achieve 4th-order noise shaping with only a 2nd-order loop filter. The proposed modulator is fabricated in a 0.13- CMOS process with an active area of 0.17 mm2. It operates at 640 MHz and achieves a peak SNDR of 80.4 dB in a 15-MHz bandwidth while consuming 11.4 mW from a 1.2-V power supply.
Autors: Taewook Kim;Changsok Han;Nima Maghari;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3248 - 3261
Publisher: IEEE
 
» A 50–66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs
Abstract:
Digital phase-locked loop (DPLL) frequency synthesizers have become popular for wireless applications in the sub-10-GHz range. However, mm-wave synthesizers still rely on analog PLLs, predominantly of the sub-harmonic, integer-N-type. This paper describes the design and implementation of a 50–66-GHz phase-domain DPLL that uses a fundamental frequency capacitively degenerated digitally controlled oscillator (DCO) with 40-kHz frequency step. Following frequency division with a modulus of only 4, a two-step 8-bit time-to-digital converter (TDC) digitizes the phase of the 12.5–16.5-GHz divider output with 450-fs resolution. Digital calibration based on the statistical element selection technique augmented by mean adaptation is used to mitigate TDC nonlinearity that results from random mismatches. Additional digital calibration techniques are introduced to mitigate DCO non-linearity and phase mismatches in the digital phase extraction sub-system, and to ensure robust operation of the inductor-less 4 frequency divider over process, voltage and temperature (PVT) variations. A 65-nm CMOS prototype of the DPLL occupies 0.45 mm2 excluding pads and consumes 46 mA from a 1-V supply. The PLL achieves best (worst) case rms jitter of 220 (302) fs, best (worst) phase noise of −83/−94.5/−122 (−79/−88/ −116) dBc/Hz at 0.1/1/10 MHz offset, and −52.2(−48.3) dBc fractional spur.
Autors: Ahmed I. Hussein;Sriharsha Vasadi;Jeyanandh Paramesh;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3329 - 3347
Publisher: IEEE
 
» A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel
Abstract:
A 1.62-to-8.1 Gb/s video interface receiver with an adaptive equalizer and a stream clock generator (SCG) is proposed. The adaptation logic is achieved by an edge-based adaptation and it controls the continuous-time linear equalizer ac boost. Using the adaptation logic, the minimum BER point is selected for several cables. The SCG consists of a phase-switching fractional divider and a delta–sigma modulator. The dividing factor is determined by the display resolution and the SCG operates up to 680 MHz which is the 4K UHD pixel frequency. The proposed receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.282 mm2. The measured BER is less than with a 20-ft-long video cable, whose insertion loss at 4.05 GHz is 20 dB. The receiver consumes 55.1 mW at the data rate of 8.1 Gb/s.
Autors: Kwanseo Park;Jinhyung Lee;Kwangho Lee;Min-Seong Choo;Sungchun Jang;Sang-Hyeok Chu;Sungwoo Kim;Deog-Kyoon Jeong;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2017, volume: 64, issue:12, pages: 1432 - 1436
Publisher: IEEE
 
» A 60-GHz 360° 5-Bit Phase Shifter With Constant IL Compensation Followed by a Normal Amplifier With ±1 dB Gain Variation and 0.6-dBm OP $_{mathrm{ -1dB}}$
Abstract:
In this brief, a concise compensation technique to obtain constant insertion loss (IL) among different phase shifting states of an millimeter-wave switch-type phase shifter (PS) is developed. The main idea is to introduce switches into the PS to align ILs of all phase states to the maximum, which hardly introduces additional phase variation, degrades IL flatness, or deteriorates maximum IL. A 60-GHz 360° 5-bit switch-type PS is designed with the proposed technique in a 65-nm CMOS technology. Measured results show that the IL variation among all 32 phase shifting states is within ±0.8 dB over 57–66 GHz, with a maximum root-mean-square (rms) phase error of 8°, a gain tuning range of 8 dB and an input 1-dB power compression point (IP−1dB) of 13 dBm. The proposed PS followed by a 60-GHz normal amplifier with invariable gain is also designed and verified. A maximum gain of 4 dB is achieved with a gain variation within ±1 dB over a 9-GHz bandwidth, an output 1-dB power compression point (OP−1dB) of 0.6 dBm, a maximum rms phase error of 11.3°, and a dc power consumption of 30 mW.
Autors: Dong Huang;Lei Zhang;Di Li;Li Zhang;Yan Wang;Zhiping Yu;
Appeared in: IEEE Transactions on Circuits and Systems II: Express Briefs
Publication date: Dec 2017, volume: 64, issue:12, pages: 1437 - 1441
Publisher: IEEE
 
» A 60-GHz SiGe BiCMOS Monostatic Transceiver for FMCW Radar Applications
Abstract:
In this paper, a high-range 60-GHz monostatic transceiver system suitable for frequency-modulated continuous-wave (FMCW) applications is presented. The RF integrated circuit is fabricated using a 0.13- SiGe BiCMOS technology with / of 250/340 GHz and occupies a very compact area of mm2. All of the internal blocks are designed fully differential with an in-phase/quadrature receiver (RX) conversion gain of 14.8 dB and −18.2 dBm of input-referred 1-dB compression point and a transmitter (TX) with 6.4 dBm of output power. The 60-GHz voltage-controlled oscillator is of a push-push type Colpitts oscillator integrated into a frequency divider with an output frequency between 910 MHz and 1 GHz with the help of 3-bit frequency tuning mechanism for external phase-locked loop operations. Between the TX and RX channels, a tunable coupler is placed to guarantee a high isolation between channels which could withstand any fabrication failures and provide a single differential antenna output. On the TX side, two power detectors are placed in order to monitor the transmitted and reflected powers on the TX channel by passing through a branch-line coupler for built-in-self-test purposes. The total current consumption of this transceiver is 156 mA at 3.3 V of single supply. Considering the successful real-time radar measurements, which the radar is able to detect the objects in more than 90-m range, it proves the suitability of this monostatic chip in high-range FMCW radar systems.
Autors: Efe Öztürk;Dieter Genschow;Uroschanit Yodprasit;Berk Yilmaz;Dietmar Kissinger;Wojciech Debski;Wolfgang Winkler;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2017, volume: 65, issue:12, pages: 5309 - 5323
Publisher: IEEE
 
» A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
Abstract:
A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-tap decision feedback equalization (DFE). The DFE, which operates at quarter-rate, features a look-ahead speculation to relax DFE timing to 4 unit-interval. The analog front end includes a transadmittance transimpedance inductorless variable gain amplifier, resulting in a low power and compact front end. The RX, wirebonded to a discrete GaAs photodiode, achieves an energy efficiency of 1.4 pJ/bit and −5-dBm optical modulation amplitude while recovering PRBS-7 data (bit-error-rate ) modulated by a VCSEL driver with a 2-tap feed forward equalization (FFE) (main + precursor) over 7 m of graded-index 50/125- multimode fiber. The measured sensitivities at 56 and 32 Gb/s are −9- and −13-dBm optical modulation amplitude, respectively.
Autors: Ilter Ozkaya;Alessandro Cevrero;Pier Andrea Francese;Christian Menolfi;Thomas Morf;Matthias Brändli;Daniel M. Kuchta;Lukas Kull;Christian W. Baks;Jonathan E. Proesel;Marcel Kossel;Danny Luu;Benjamin G. Lee;Fuad E. Doany;Mounir Meghelli;Yusuf L
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3458 - 3473
Publisher: IEEE
 
» A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving −164-dBFS/Hz NSD
Abstract:
An oversampled continuous-time (CT) pipeline ADC clocked at 9 GHz achieving 1.125-GHz bandwidth and −164 dBFS/Hz average small-signal noise density is presented. In contrast to traditional discrete-time (DT) pipeline ADCs, the system processes the signals in CT form throughout all the pipeline stages and thus sampling-induced artifacts such as aliasing and high-peak ADC driving current are mitigated. Despite the oversampled nature of the ADC, its digitization bandwidth is on par with that of traditional non-interleaved DT pipeline ADCs since CT signal processing is not constrained by settling time requirements. The ADC was fabricated in a 28-nm CMOS process technology and consumes 2.3 W.
Autors: Hajime Shibata;Victor Kozlov;Zexi Ji;Asha Ganesan;Haiyang Zhu;Donald Paterson;Jialin Zhao;Sharvil Patil;Shanthi Pavan;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3219 - 3234
Publisher: IEEE
 
» A 95-nm-wide Tunable Two-Mode Vertical External Cavity Surface-Emitting Laser
Abstract:
We report on a wide tunability of an optically pumped semiconductor vertical external cavity surface-emitting laser with a unique two-mode resonant microcavity. Using only high-reflectivity mirrors in the resonator and controlling the active region temperature by readjustment of pump power and heat extraction, we have demonstrated a record 95-nm wavelength-tuning range. Laser center wavelength was 985 nm.
Autors: Artur Broda;Anna Wójcik-Jedlińska;Iwona Sankowska;Michał Wasiak;Marta Wieckowska;Jan Muszalski;
Appeared in: IEEE Photonics Technology Letters
Publication date: Dec 2017, volume: 29, issue:24, pages: 2215 - 2218
Publisher: IEEE
 
» A Backscattering-Suppression-Based Variational Level-Set Method for Segmentation of SAR Oil Slick Images
Abstract:
Robust and accurate segmentation of oil slick regions from synthetic aperture radar satellite images plays a fundamental role for detecting and monitoring of oil spills. However, uneven intensity, high noise, and blurry boundary, which always exist in oil spill images, make the automatic segmentation of such images very difficult. In this paper, a two-stage method is developed for the segmentation of oil spill images. The first stage of our method is to obtain the enhanced image by suppressing the backscattering from an oil spill image. Once the enhanced image is obtained, then in the second stage, a variational segmentation model is presented for dealing with the enhanced image. The data term of the energy functional is constructed for the enhanced image in a piecewise constant way. In addition, a Cahn–Hilliard-type regularization term is introduced into the energy functional. The variational model is numerically solved by alternating minimization. Numerical experiments on oil spill images from ENVISAT show that the proposed method can obtain an overall accuracy of for dark spot segmentation and create limited false alarms and outperforms the two representative state-of-the-art methods in terms of the efficiency and accuracy.
Autors: Yongfei Wu;Chuanjiang He;Yang Liu;Moting Su;
Appeared in: IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
Publication date: Dec 2017, volume: 10, issue:12, pages: 5485 - 5494
Publisher: IEEE
 
» A Beam Steering Based Hybrid Precoding for MU-MIMO mmWave Systems
Abstract:
We propose a hybrid precoding scheme for downlink multi-user multiple-input multiple-output (MU-MIMO) millimeter-wave (mmWave) systems. Firstly, the proposed precoder is designed by the beam steering condition and the zero-interference condition, which can be obtained with the information of angles of departure (AoDs) in frequency division duplex (FDD) systems. Then, the proposed precoder is decomposed into the radio frequency (RF) precoder and the baseband precoder without the loss of response. Also, array response vector selection algorithm is proposed to prevent the sum rate degradation in numerous users region. Simulation results show that the sum rate of the proposed hybrid precoder is higher than those of the block diagonalization (BD) based schemes in the region of more than 5 users and approaches the sum rate of the beam steering scheme without MU interference as the number of base station (BS) antennas increases.
Autors: Yongjin Ahn;Taeyoung Kim;Chungyong Lee;
Appeared in: IEEE Communications Letters
Publication date: Dec 2017, volume: 21, issue:12, pages: 2726 - 2729
Publisher: IEEE
 
» A Belief-Evolution-Based Approach for Online Control of Fuzzy Discrete-Event Systems Under Partial Observation
Abstract:
In this paper, we investigate the partially observed supervisor synthesis problem in the framework of fuzzy discrete-event systems (DESs). The goal is to synthesize a fuzzy supervisor such that the behavior of the closed-loop system is within a given fuzzy language. A new approach for solving this problem is proposed based on the idea of belief evolution. Specifically, we propose an algorithm that can be implemented in an online manner. We show that the proposed algorithm is both sound and complete, i.e., it effectively solves the supervisor synthesis problem. To the best of our knowledge, this is the first algorithm with such a property for fuzzy DESs, as previous works on this topic mostly focus on the supervisor existence condition rather than the supervisor synthesis problem.
Autors: Xiang Yin;
Appeared in: IEEE Transactions on Fuzzy Systems
Publication date: Dec 2017, volume: 25, issue:6, pages: 1830 - 1836
Publisher: IEEE
 
» A Better Model for Job Redundancy: Decoupling Server Slowdown and Job Size
Abstract:
Recent computer systems research has proposed using redundant requests to reduce latency. The idea is to replicate a request so that it joins the queue at multiple servers. The request is considered complete as soon as any one of its copies completes. Redundancy allows us to overcome server-side variability–the fact that a server might be temporarily slow due to factors such as background load, network interrupts, and garbage collection to reduce response time. In the past few years, queueing theorists have begun to study redundancy, first via approximations, and, more recently, via exact analysis. Unfortunately, for analytical tractability, most existing theoretical analysis has assumed an Independent Runtimes (IR) model, wherein the replicas of a job each experience independent runtimes (service times) at different servers. The IR model is unrealistic and has led to theoretical results that can be at odds with computer systems implementation results. This paper introduces a much more realistic model of redundancy. Our model decouples the inherent job size () from the server-side slowdown (), where we track both and for each job. Analysis within the model is, of course, much more difficult. Nevertheless, we design a dispatching policy, Redundant-to-Idle-Queue, which is both analytically tractable within the model and has provably excellent performance.
Autors: Kristen Gardner;Mor Harchol-Balter;Alan Scheller-Wolf;Benny Van Houdt;
Appeared in: IEEE/ACM Transactions on Networking
Publication date: Dec 2017, volume: 25, issue:6, pages: 3353 - 3367
Publisher: IEEE
 
» A Cable-Driven Flexible Robotic Grasper With Lego-Like Modular and Reconfigurable Joints
Abstract:
This paper proposes a modular and reconfigurable cable-driven robotic grasper (MoReCa grasper) for grasping diverse unknown objects in unstructured environments, which integrates the characteristics of full actuation and underactuation. The mechanical design of this robotic grasper is introduced with a focus on its Lego-like modular design feature and reconfigurable flexible joints. With these features, the length of this robotic grasper can be arbitrarily changed through the addition or removal of the Lego-like finger modules connected by magnets without rerouting or breaking the cables. The shape and degree of freedom of the robotic grasper can be adjusted by changing the states of the joints using embedded clutches. When the joints are locked, the grasper can maintain its shape without additional power from actuators leading to better energy efficiency. The kinematics, workspace, and contact force are analyzed. On this basis, an automatically reshaping method (ARM) based on the motor's current during the operation is proposed. Lastly, an example prototype of the robotic grasper with two fingers (four modules each) is built and tested. In the first experiment, the maximum grasping force is obtained. The second experiment demonstrates the ability of grasping diverse objects via changing the number of the modules and presetting the shape of the robotic grasper. The effectiveness of the ARM is verified in the third experiment.
Autors: Changsheng Li;Xiaoyi Gu;Hongliang Ren;
Appeared in: IEEE/ASME Transactions on Mechatronics
Publication date: Dec 2017, volume: 22, issue:6, pages: 2757 - 2767
Publisher: IEEE
 
» A Capstone Design Project on the Development of a Prototype Near-Field Antenna Measurement System [Education Corner]
Abstract:
This article presents the capstone design project of four final-year electrical and computer engineering undergraduate students, which focused on the development of a nearfield antenna measurement system from the ground up. The aim of this article is 1) to demonstrate that a prototype near-field antenna measurement system can be developed as a final-year capstone design project and 2) to show that the development of such a prototype can engage students with a multidisciplinary engineering design. To this end, this article discusses all the subsystems designed by the students to achieve full functionality for this prototype near-field antenna measurement system. Finally, the experimental validation of the system is presented, along with discussions on how to use this system for educational and research activities.
Autors: Chen Niu;Brent Schellenberg;Michael Kleiber;Jasper Taylor;Ahmad Byagowi;Puyan Mojabi;
Appeared in: IEEE Antennas and Propagation Magazine
Publication date: Dec 2017, volume: 59, issue:6, pages: 118 - 127
Publisher: IEEE
 
» A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM
Abstract:
DRAM cells in close proximity can fail depending on the data content in neighboring cells. These failures are called data-dependent failures. Detecting and mitigating these failures online while the system is running in the field enables optimizations that improve reliability, latency, and energy efficiency of the system. All these optimizations depend on accurately detecting every possible data-dependent failure that could occur with any content in DRAM. Unfortunately, detecting all data-dependent failures requires the knowledge of DRAM internals specific to each DRAM chip. As internal DRAM architecture is not exposed to the system, detecting data-dependent failures at the system-level is a major challenge. Our goal in this work is to decouple the detection and mitigation of data-dependent failures from physical DRAM organization such that it is possible to detect failures without knowledge of DRAM internals. To this end, we propose MEMCON , a memory content-based detection and mitigation mechanism for data-dependent failures in DRAM. MEMCON does not detect every possible data-dependent failure. Instead, it detects and mitigates failures that occur with the current content in memory while the programs are running in the system. Using experimental data from real machines, we demonstrate that MEMCON is an effective and low-overhead system-level detection and mitigation technique for data-dependent failures in DRAM.
Autors: Samira Khan;Chris Wilkerson;Donghyuk Lee;Alaa R. Alameldeen;Onur Mutlu;
Appeared in: Computer Architecture Letters
Publication date: Dec 2017, volume: 16, issue:2, pages: 88 - 93
Publisher: IEEE
 
» A Catalytic Conversion: Westcom Showcases Her Science Talents
Abstract:
Twenty-three-year-old Alayna Westcom stood onstage in a white dress with a blue atom emblem, blue shoes, and lab glasses. On a table covered by a white tablecloth, she added hydrogen peroxide and potassium iodide to a little soap and then stepped back to watch. "Don't try this at home," she teased as white foam erupted onto the stage. It was a catalytic decomposition reaction that goes by the nickname "elephant's toothpaste." The hydrogen peroxide rapidly decomposes into water and oxygen gas, and when the gas gets trapped in the soap, voilá-bubbles, and a huge shot of foam.
Autors: Katianne Williams;
Appeared in: IEEE Women in Engineering Magazine
Publication date: Dec 2017, volume: 11, issue:2, pages: 24 - 25
Publisher: IEEE
 
» A Circuit-Based Approach for Characterizing High Frequency Electromigration Effects
Abstract:
A test chip for studying electromigration (EM) effects under various dc and ac stress conditions was implemented in a 32-nm-high-k metal gate process. The stress current, which can be either dc, pulsed dc, square ac, or real ac, was generated on-chip and applied to 60 devices under test (DUTs) in parallel. An on-chip voltage-controlled oscillator was designed to generate a stress frequency higher 1 GHz while on-chip metal gate heaters were used to raise the DUT temperature to >300 °C for accelerated testing. Both abrupt and progressive failures were observed under dc and pulsed dc stress modes. The abrupt failures could be further divided into two categories based on the final resistance value. Although no ac stress induced failures were observed during our extensive stress experiments, ac stress did have an impact on the subsequent dc EM lifetime. Two possible scenarios are given to explain the high frequency EM results.
Autors: Chen Zhou;Xiaofei Wang;Rita Fung;Shi-Jie Wen;Richard Wong;Chris H. Kim;
Appeared in: IEEE Transactions on Device and Materials Reliability
Publication date: Dec 2017, volume: 17, issue:4, pages: 763 - 772
Publisher: IEEE
 
» A Class-G Voltage-Mode Doherty Power Amplifier
Abstract:
This paper presents the combination of two back-off efficiency enhancement techniques, the voltage-mode Doherty and the class-G switched-capacitor power amplifier (PA), to achieve efficiency peaking at both 6 and 12 dB back off without introducing the mode-switching glitches present in previous architectures. The proposed technique enables transmission of high peak-to-average-power ratio (PAPR) signals with high efficiency while maintaining excellent linearity. The PA is fabricated in 45-nm CMOS SOI with integrated balun for power combining and matching. At 3.5 GHz a saturated output power of 25.3 dBm is measured with 30.4%/25.3%/17.4% power added efficiency (PAE) at 0/6/12 dB back off. With memoryless, non-adaptive linearization, the PA achieves 19.2% PAE with −35.8 dB error vector magnitude (EVM) while transmitting a 40 MHz 256-QAM 10.1 dB PAPR 802.11ac modulation. Significant efficiency improvement compared to class-B and EVM better than −34 dB is maintained over more than 1 GHz bandwidth.
Autors: Voravit Vorapipat;Cooper S. Levy;Peter M. AsbeckIEEE;
Appeared in: IEEE Journal of Solid-State Circuits
Publication date: Dec 2017, volume: 52, issue:12, pages: 3348 - 3360
Publisher: IEEE
 
» A Collaborative Learning Culture: Preparing K-12 Teachers for STEM Success [Pipelining: Attractive Programs for Women]
Abstract:
After teaching elementary and middle school science and art for just under a decade, Wendy Binder was looking for a challenge. With her unusual combination of bachelor's degrees in biology and chemistry, a master's of science in education, and experience teaching at the elementary school level, she first found career success as a curriculum developer for the National Science Resources Center, a joint venture between the Smithsonian and the National Academies. When the National Science Teachers Association (NSTA) decided to create a professional development department, Binder became its first hire by the department director. In her ten years there, she has worked with industry partners to implement sustainable programs that help teachers give students opportunities to learn the hard and soft skills they will need to be competitive in the science, technology, engineering, and mathematics (STEM) workforce.
Autors: Katianne Williams;
Appeared in: IEEE Women in Engineering Magazine
Publication date: Dec 2017, volume: 11, issue:2, pages: 44 - 46
Publisher: IEEE
 
» A Combined Power and Fault Analysis Attack on Protected Grain Family of Stream Ciphers
Abstract:
Differential fault analysis of stream ciphers, such as Grain (Grain v1 and Grain-128) has been an active area of research. Several countermeasures to thwart such analysis have been also proposed in the related cryptographic literature. In this paper, we demonstrate a novel combination of power and fault analysis strategies to devise attacks against such protected implementations of Grain stream cipher. We considered clock glitch induced faults occurring in practice to construct our fault model. In addition, we developed a generic power analysis attack technique against the Grain family of stream ciphers assuming that the cipher implementation can be resynchronized multiple times with a fixed secret key and any randomly generated initialization vector. Subsequently, we combine our proposed power analysis strategy with the notion of the practically occurring faults to mount attacks on various fault attack countermeasures. In order to validate our proposed power analysis attack, we report the results of power trace classifications of a Grain v1 implementation on SASEBO-GII board. The captured power traces were analyzed using least squares support vector machine learning algorithm-based multiclass classifiers to segregate the power traces into the respective Hamming distance (HD) classes. To extract power samples with high information about HD classes, signal-to-noise ratio (SNR) metric was chosen for feature selection. The experimental results of power trace classifications of test set showed success rate as high as 92.5% when the seven largest SNR sample instants over a clock cycle were chosen as features along with a suitable kernel hyperparameter combination.
Autors: Abhishek Chakraborty;Bodhisatwa Mazumdar;Debdeep Mukhopadhyay;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Dec 2017, volume: 36, issue:12, pages: 1968 - 1977
Publisher: IEEE
 
» A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in FPGA
Abstract:
Due to the conventional look-up-table (LUT) using the static random access memory (SRAM) cell, field programmable gate arrays (FPGAs) almost reach the limitation in term of the density, speed, and configuration overhead. This paper proposes an improved memristor-based LUT (MLUT) circuit which is compatible with the mainstream LUT circuit in FPGA. Any arbitrary combined logic functions can be implemented in the MLUT through specific configurations. Then the MLUT shows superior advantages over the conventional LUT such as smaller area overhead and fewer data transmission. As a case study, a one-bit full adder is simulated to verify that the design is of practice in PSPICE. Moreover, the adder can be cascaded into multibit full adder demonstrating competitiveness against the conventional configurable logic block in FPGA technology. MLUT can be a candidate to replace the conventional SRAM-based LUT and further improves the performance of FPGAs.
Autors: Yanwen Guo;Xiaoping Wang;Zhigang Zeng;
Appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication date: Dec 2017, volume: 36, issue:12, pages: 2144 - 2148
Publisher: IEEE
 
» A Compact Quasi-Static Terminal Charge and Drain Current Model for Double-Gate Junctionless Transistors and Its Circuit Validation
Abstract:
Junctionless transistors (JLTs) are presumed more scalable compared to other technologies, but its circuit performance is not fully understood. In this paper, we develop a charge-based compact model for a double-gate JLT(DGJLT) to explore the dc and the quasi-static performance of the transistor technology. First, 1-D Poisson’s equation is solved analytically by using the Lambert function to obtain the (sheet) charge density in the channel. Second, a continuous charge-based drain current model is derived for long-channel DGJLTs using the Pao-Sah’s dual integral. The model applies to all working regions (i.e., fully depleted, partly depleted, and accumulation). Third, based on the drain current, we develop the terminal charge model for ac and transient circuit simulation. Finally, the short-channel effect is modeled by adding an effective gate voltage to the proposed long-channel model. The compact model is validated by a numerical simulator over a wide range of voltage bias and device geometries. Results predicted by the analytical model agree well with numerical results. The model has been implemented in the Hspice circuit simulator with Verilog-A language and used to simulate a DGJLT inverter and oscillator without any convergence problem.
Autors: Chunsheng Jiang;Renrong Liang;Jun Xu;Muhammad Ashraful Alam;
Appeared in: IEEE Transactions on Electron Devices
Publication date: Dec 2017, volume: 64, issue:12, pages: 4823 - 4830
Publisher: IEEE
 
» A Comparative Study of InGaP/GaAs Collector-Up HBTs for High-Reliability Small-Scale PA Applications
Abstract:
In this paper, the characteristics of InGaP/GaAs collector-up (C-up) pnp and npn heterojunction bipolar transistors (HBTs) with the graded InGaAs base and the nonuniform doped collector are demonstrated, and the performances as well as the reliability of the novel HBTs have been compared with the conventional InGaP/GaAs HBTs with various collector structures and thermal schemes. Compared to conventional HBTs, the studied C-up HBTs exhibited better current-driving capability, higher RF efficiency, and improved long-term reliability. Note that the pnp device displayed greater thermal stability enhancements, which are distinct and reproducible, than the npn device. The favorable data of the pnp C-up HBT could be attributed to higher electron mobility, resulting in low base resistance and higher emitter resistance improving the thermal stability. The comparison results, based on pragmatic observations from the C-up HBTs without relatively large heat-dissipation configurations, should be very useful for the reliable and the cost-effective design as small-scale power amplifiers in the wideband CDMA system.
Autors: Jer-Lin Su;Hsien-Cheng Tseng;
Appeared in: IEEE Transactions on Device and Materials Reliability
Publication date: Dec 2017, volume: 17, issue:4, pages: 678 - 682
Publisher: IEEE
 
» A Comparative Study of Methods for Estimating Virtual Flux at the Point of Common Coupling in Grid-Connected Voltage Source Converters With LCL Filter
Abstract:
Grid synchronization based on virtual flux (VF) estimation allows for control of grid-connected power converter without depending on ac-voltage measurements. This is useful in voltage-sensor-less applications for reducing cost and complexity of the control hardware, and can be utilized in case of limited reliability or availability of voltage measurements at the intended point of synchronization to the grid. However, for voltage source converters (VSC) with LCL filters, the influence of the capacitor current must be taken into account to ensure accurate VF estimation at the point of common coupling (PCC) with the grid. This paper presents a comparative evaluation of three VF-based methods for grid synchronization of VSCs with LCL filters, with three different ways of obtaining the capacitor current. The VF estimation in the first method is based only on the measured converter currents. The second method includes capacitor voltage measurements used for estimating the capacitor currents, while the capacitor currents are measured in the third approach. Comparative results from time-domain simulations are presented, demonstrating good performance of the estimation and accurate control of the active and reactive power at the PCC with all three methods, as long as sufficiently accurate filter parameters and current measurements are available. However, the approach based on capacitor current measurements is sensitive to noise due to the high ripple current compared with the fundamental frequency current in the capacitors. The operation of a converter with VF-based grid synchronization including estimation of the capacitor current is demonstrated by experimental results, verifying the voltage sensor-less operation with LCL filter.
Autors: Nurul Fazlin Roslan;Jon Are Suul;Joan Rocabert;Pedro Rodriguez;
Appeared in: IEEE Transactions on Industry Applications
Publication date: Dec 2017, volume: 53, issue:6, pages: 5795 - 5809
Publisher: IEEE
 
» A Comparison Between Electrical Capacitance Tomography and Displacement-Current Phase Tomography
Abstract:
We compare electrical capacitance tomography (ECT) and displacement-current phase tomography (DCPT) results for non-invasive imaging of lossy media. ECT is based on mutual capacitance measurements between electrode pairs surrounding the region of interest (RoI), whereas DCPT is a relatively less mature sensing modality that utilizes the phase information inherent in the displacement current measured by such electrode pairs excited by time-harmonic voltages (in the electroquasistatic regime). DCPT and ECT can be implemented using basically the same hardware components and used alongside to provide complementary information for imaging purposes or separately to reconstruct the spatial distribution of the loss tangent or the permittivity within the RoI, respectively. We show that the (nonlinear) relationship between the measured phase in DCPT and the conductivity distribution in the RoI has a more extended linear range than the nonlinear relationship between the measured capacitances in ECT and the permittivity distribution in the RoI. Of note, DCPT does not require electrical contact with the RoI in contrast to electrical impedance tomography. To illustrate the potential of DCPT, we evaluate its performance using both numerical examples and experiment results.
Autors: Cagdas Gunes;Qussai M. Marashdeh;Fernando L. Teixeira;
Appeared in: IEEE Sensors Journal
Publication date: Dec 2017, volume: 17, issue:24, pages: 8037 - 8046
Publisher: IEEE
 
» A Comparison of Feature Representations for Explosive Threat Detection in Ground Penetrating Radar Data
Abstract:
The automatic detection of buried threats in ground penetrating radar (GPR) data is an active area of research due to GPR’s ability to detect both metal and nonmetal subsurface objects. Recent work on algorithms designed to distinguish between threats and nonthreats in GPR data has utilized computer vision methods to advance the state-of-the-art detection and discrimination performance. Feature extractors, or descriptors, from the computer vision literature have exhibited excellent performance in representing 2-D GPR image patches and allow for robust classification of threats from nonthreats. This paper aims to perform a broad study of feature extraction methods in order to identify characteristics that lead to improved classification performance under controlled conditions. The results presented in this paper show that gradient-based features, such as the edge histogram descriptor and the scale invariant feature transform, provide the most robust performance across a large and varied data set. These results indicate that various techniques from the computer vision literature can be successfully applied to target detection in GPR data and that more advanced techniques from the computer vision literature may provide further performance improvements.
Autors: Rayn Sakaguchi;Kenneth D. Morton;Leslie M. Collins;Peter A. Torrione;
Appeared in: IEEE Transactions on Geoscience and Remote Sensing
Publication date: Dec 2017, volume: 55, issue:12, pages: 6736 - 6745
Publisher: IEEE
 
» A Comparison of Indoor MIMO Measurements and Ray-Tracing at 24 and 2.55 GHz
Abstract:
Colocated multiple-input multiple-output measurements at 2.55 and 24 GHz are presented for two university buildings consisting of classrooms and offices. Link gain in hallways and connected laboratories looks similar at the two frequencies when the effect of lower effective receive antenna aperture with increasing frequency is removed. Non-line-of-sight (NLOS) propagation through a wall or around hallway corners exhibits approximately 5–20 dB (11 dB on average) greater loss beyond the 20 dB aperture loss at 24 GHz compared to that at 2.55 GHz. Fixed directional antennas increase path loss (PL) by an average of 13 dB when misaligned. Capacity for normalized signal-to-noise ratio is very similar in the two bands and is close to that for the optimal independent identically distributed case, indicating sufficient multipath for spatial multiplexing at 24 GHz. A ray-tracing study suggests that material loss must increase from 2.55 to 24 GHz to correctly predict the higher PL at 24 GHz in severely obstructed scenarios, indicating a need for future material characterization in high microwave bands. The results suggest that 24 GHz is a viable option to replace medium-range (10–30 m) NLOS wireless services currently operating at 2.4 GHz.
Autors: Jon W. Wallace;Waseh Ahmad;Yahan Yang;Rashid Mehmood;Michael A. Jensen;
Appeared in: IEEE Transactions on Antennas and Propagation
Publication date: Dec 2017, volume: 65, issue:12, pages: 6656 - 6668
Publisher: IEEE
 
» A Comprehensive Evaluation of Software Rejuvenation Policies for Transaction Systems With Markovian Arrivals
Abstract:
Software rejuvenation is one of the proactive fault management techniques to prevent system performance degradation, which may lead to the system failure caused by software aging. In the design of software rejuvenation, it is important to determine the optimal timing of triggering the rejuvenation in terms of the system overhead. In this paper, we consider six software rejuvenation policies, which are categorized into time-based and workload-based policies, under the environment where the arrival stream of system follows a Markovian arrival process (MAP). After building the stochastic models with respective rejuvenation policies, we formulate the loss probability of transaction and the upper bound of mean response time as the system performance indices. In the numerical illustrations, we exhibit a comprehensive study to compare six software rejuvenation policies numerically and show that the proposed rejuvenation policies called wait-time policies are superior to the others under the MAP arrival stream.
Autors: Junjun Zheng;Hiroyuki Okamura;Lin Li;Tadashi Dohi;
Appeared in: IEEE Transactions on Reliability
Publication date: Dec 2017, volume: 66, issue:4, pages: 1157 - 1177
Publisher: IEEE
 
» A Comprehensive Forwarding Strategy in DTNs: Theory and Practice
Abstract:
Delay tolerant networks (DTNs) are featured by unpredictable mobility patterns and easily interrupted connections. Forwarding strategy has always been the research focus in DTNs, in order to improve a delivery ratio. An enormous amount of research works pay attention to solving the following two problems: whether to forward and how to forward. Therefore, forwarding metrics and forwarding strategies both play important roles in DTNs. In this paper, we consider a generalized random-waypoint model with heterogeneous nodes; the node's speed is regarded as the forwarding metric, which includes both short-term and long-term speed. Subsequently, we propose a theoretical, multicopy delegation forwarding based on short-term and long-term speed in DTNs (DFSL-T), which first determines a comprehensive mapping from short-term speed and long-term speed to the actual forwarding metric. Then, according to the forwarding metric and delegation forwarding strategy, DFSL-T utilizes some efficient nodes with higher forwarding metrics to assist in delivering messages, in order to improve the delivery ratio while reducing the forwarding cost. However, DFSL-T assumes that each node could achieve the average speeds of the others, which is impractical. In order to overcome this problem, we further propose a practical strategy (DFSL-P) through exchanging and evaluating the average speeds of each other. Finally, we conduct simulations based on the synthetic mobility pattern and real trace. The results show that compared with other multicopy forwarding strategies, DFSL-T and DFSL-P achieve higher forwarding efficiency, which is the result of delivery ratio divided by forwarding cost.
Autors: En Wang;Yongjian Yang;Jie Wu;Wenbin Liu;
Appeared in: IEEE Transactions on Vehicular Technology
Publication date: Dec 2017, volume: 66, issue:12, pages: 11220 - 11232
Publisher: IEEE
 
» A Computational Study of Vocal Fold Dehydration During Phonation
Abstract:
While vocal fold dehydration is often considered an important factor contributing to vocal fatigue, it still remains unclear whether vocal fold vibration alone is able to induce severe dehydration that has a noticeable effect on phonation and perceived vocal effort. A three-dimensional model was developed to investigate vocal fold systemic dehydration and surface dehydration during phonation. Based on the linear poroelastic theory, the model considered water resupply from blood vessels through the lateral boundary, water movement within the vocal folds, water exchange between the vocal folds and the surface liquid layer through the epithelium, and surface fluid accumulation and discharge to the glottal airway. Parametric studies were conducted to investigate water loss within the vocal folds and from the surface after a 5-min sustained phonation under different permeability and vibration conditions. The results showed that the dehydration generally increased with increasing vibration amplitude, increasing epithelial permeability, and reduced water resupply. With adequate water resupply, a large-amplitude vibration can induce an overall systemic dehydration as high as 3%. The distribution of water loss within the vocal folds was non-uniform, and a local dehydration higher than 5% was observed even under conditions of a low overall systemic dehydration (<1%). Such high level of water loss may severely affect tissue properties, muscular functions, and phonations characteristics. In contrast, water loss of the surface liquid layer was generally an order of magnitude higher than water loss inside the vocal folds, indicating that the surface dehydration level is likely not a good indicator of the systemic dehydration.
Autors: Liang Wu;Zhaoyan Zhang;
Appeared in: IEEE Transactions on Biomedical Engineering
Publication date: Dec 2017, volume: 64, issue:12, pages: 2938 - 2948
Publisher: IEEE
 
» A Consensus Process [Standards News]
Abstract:
Addresses the concept of consensus when discussing the development of standards. A Consensus Process Standards are a consensus opinion of a group of subject matter experts (SMEs) who document and share their skills with the general users, who may not be experts. Standards are learnings based on the past to provide directions for the future. Standards are the language used by SMEs to pass their experience and knowledge to the users. What is consensus? Business Dictionary defines consensus as Middle ground in decision making, between total assent and total disagreement. Consensus depends on participants having shared values and goals, and on having broad agreement on specific issues and overall direction. Consensus implies that everyone accepts and supports the decision, and understands the reasons for making it.
Autors: Daleep Mohla;
Appeared in: IEEE Industry Applications Magazine
Publication date: Dec 2017, volume: 23, issue:6, pages: 71 - 81
Publisher: IEEE
 
» A Context-Aware Architecture Supporting Service Availability in Mobile Cloud Computing
Abstract:
Mobile systems are gaining more and more importance, and new promising paradigms like Mobile Cloud Computing are emerging. Mobile Cloud Computing provides an infrastructure where data storage and processing could happen outside the mobile node. Specifically, there is a major interest in the use of the services obtained by taking advantage of the distributed resource pooling provided by nearby mobile nodes in a transparent way. This kind of systems is useful in application domains such as emergencies, education and tourism. However, these systems are commonly based on dynamic network topologies, in which disconnections and network partitions can occur frequently, and thus the availability of the services is usually compromised. Techniques and methods from Autonomic Computing can be applied to Mobile Cloud Computing to build dependable service models taking into account changes in the context. In this work, a context-aware software architecture is proposed to support the availability of the services deployed in mobile and dynamic network environments. The proposal is based on a service replication scheme together with a self-configuration approach for the activation/hibernation of the replicas of the service depending on relevant context information from the mobile system. To that end, an election algorithm has been designed and implemented.
Autors: Gabriel Guerrero-Contreras;José Luis Garrido;Sara Balderas-Díaz;Carlos Rodríguez-Domínguez;
Appeared in: IEEE Transactions on Services Computing
Publication date: Dec 2017, volume: 10, issue:6, pages: 956 - 968
Publisher: IEEE
 
» A Control Scheme to Minimize Muscle Energy for Power Assistant Robotic Systems Under Unknown External Perturbation
Abstract:
This paper proposes a novel control method to minimize muscle energy for power-assistant robotic systems that support the intended motions of a user under unknown external perturbations, using surface electromyogram (sEMG) signals. Conventional control methods based on force/torque (F/T) sensors have limitations to detect human intentions and could, presumably, misunderstand or distort such intentions because of external perturbations of the interaction forces, such as those found in activities of daily living. F/T sensors measure the sum of the applied force, including unknown external forces and human intention; thus, a power-assistant robot controller cannot exactly decompose the real human force. In this paper, we describe a counterexample that cannot be supported by conventional force-sensor-based control methods. We also verify why these control methods may guide human behavior in the wrong direction, and thus, have limitations under unknown external perturbations. We then propose a new control method to minimize the muscle energy indicated by sEMG signals. The proposed control approach is fundamentally based on the concept of power-assistance, in which a robot can reduce the users expended muscle energy while performing given tasks. The proposed control approach is verified through experiments using a power-assistant robotic system for the upper limbs under external perturbations.
Autors: Jaemin Lee;Minkyu Kim;Keehoon Kim;
Appeared in: IEEE Transactions on Neural Systems and Rehabilitation Engineering
Publication date: Dec 2017, volume: 25, issue:12, pages: 2313 - 2327
Publisher: IEEE
 
» A Data-Driven Robustness Algorithm for the Internet of Things in Smart Cities
Abstract:
The Internet of Things has been applied in many fields, especially in smart cities. The failure of nodes brings a significant challenge to the robustness of topologies. The IoT of smart cities is increasingly producing a vast amount different types of data, which includes the node's geographic information, neighbor list, sensing data, and so on. Thus, how to improve the robustness of topology against malicious attacks based on big data of smart cities becomes a critical issue. To tackle this problem, this article proposes an approach to improve the robustness of network topology based on a multi-population genetic algorithm (MPGA). First, the geographic information and neighbor list of nodes are extracted from a big data server. Then a novel MPGA with a crossover operator and a mutation operator is proposed to optimize the robustness of topology. Our algorithm keeps the initial degree of each node unchanged such that the optimized topology will not increase the energy cost of adding edges. The extensive experiment results show that our algorithm can significantly improve the robustness of topologies against malicious attacks.
Autors: Tie Qiu;Jie Liu;Weisheng Si;Min Han;Huansheng Ning;Mohammed Atiquzzaman;
Appeared in: IEEE Communications Magazine
Publication date: Dec 2017, volume: 55, issue:12, pages: 18 - 23
Publisher: IEEE
 
» A DC-90-GHz 4- $V_{mathrm{ pp}}$ Modulator Driver in a 0.13- $mu text{m}$ SiGe:C BiCMOS Process
Abstract:
In this paper, a linear driver for optical modulators in a 0.13- SiGe:C BiCMOS technology with of 300/500 GHz is presented. The design is implemented following a distributed amplifier topology in a differential manner. The driver features a small-signal gain of 12.5 dB and a 3-dB bandwidth of 90 GHz and delivers a maximum output amplitude of to a 100- differential load. Delivering the maximum output swing, the large-signal gain is 10.5 dB. Time-domain measurements are performed, showing the maximum output swing with ON–OFF keying (OOK) eye-diagrams up to 64 Gb/s and pulse amplitude modulation-4 up to 45 Gbaud (90 Gb/s). Moreover, OOK eye-diagrams up to 120 Gb/s are reported with an output swing of . Total harmonic distortion measurements are also conducted demonstrating a value of 5% at 1 and 8 GHz up to an input amplitude of 800 mVppd. Using a reduced number of stages in the design, the power dissipation of the integrated circuit is 550 mW, resulting in an output power to power dissipation ratio of 3.6%. To the best knowledge of the authors, this is the first time a linear driver for optical modulators demonstrates such high bandwidth and efficiency for the demonstrated data-rates.
Autors: Pedro Rito;Iria García López;Ahmed Awny;Minsu Ko;Ahmet Cagri Ulusoy;Dietmar Kissinger;
Appeared in: IEEE Transactions on Microwave Theory and Techniques
Publication date: Dec 2017, volume: 65, issue:12, pages: 5192 - 5202
Publisher: IEEE
 
» A Decentralized Control Strategy for Economic Operation of Autonomous AC, DC, and Hybrid AC/DC Microgrids
Abstract:
Economic operation is a major concern for microgrids (MGs). System operation cost is optimized when the incremental costs (ICs) of all distributed generators (DGs) reach equality. Conventionally, economic dispatch of DGs is solved by centralized control with optimization algorithms or distributed control with consensus algorithms. To improve the reliability, scalability, and economy of MGs, a fully decentralized economic power sharing strategy is proposed in this paper. As frequency is a global state in ac MG and dc bus voltage serves as a natural indicator in dc MG, a frequency-IC droop scheme is proposed for ac MG, a voltage-IC droop scheme is proposed for dc MG, and a normalization scheme is proposed for hybrid ac/dc MG. By using the proposed technique, ICs of DGs reach equality with the convergence of the system global indicator (frequency or dc bus voltage). Then power sharing of each DG is automatically achieved based on its relevant IC function and the total operating cost can be optimized without any communication or central controllers. The proposed approach is implemented in an ac MG, a dc MG, and a hybrid ac/dc MG in MATLAB/Simulink to verify its effectiveness.
Autors: Qianwen Xu;Jianfang Xiao;Peng Wang;Changyun Wen;
Appeared in: IEEE Transactions on Energy Conversion
Publication date: Dec 2017, volume: 32, issue:4, pages: 1345 - 1355
Publisher: IEEE
 
» A Deep-Learning-Based Forecasting Ensemble to Predict Missing Data for Remote Sensing Analysis
Abstract:
The problem of missing data in remote sensing analysis is manifold. The situation becomes more serious during multitemporal analysis when data at various a-periodic timestamps are missing. In this work, we have proposed a deep-learning-based framework (Deep-STEP_FE) for reconstructing the missing data to facilitate analysis with remote sensing time series. The idea is to utilize the available data from both earlier and subsequent timestamps, while maintaining the causality constraint in spatiotemporal analysis. The framework is based on an ensemble of multiple forecasting modules, built upon the observed data in the time-series sequence. The coupling between the forecasting modules is accomplished with the help of dummy data, initially predicted using the earlier part of the sequence. Then, the dummy data are progressively improved in an iterative manner so that it can best conform to the next part of the sequence. Each of the forecasting modules in the ensemble is based on Deep-STEP, a variant of the deep stacking network learning approach. The work has been validated using a case study on predicting the missing images in normalized difference vegetation index time series, derived from Landsat-7 TM-5 satellite imagery over two spatial zones in India. Comparative performance analysis demonstrates the effectiveness of the proposed forecasting ensemble.
Autors: Monidipa Das;Soumya K. Ghosh;
Appeared in: IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
Publication date: Dec 2017, volume: 10, issue:12, pages: 5228 - 5236
Publisher: IEEE
 
» A Delay Time Model With Multiple Defect Types and Multiple Inspection Methods
Abstract:
We develop delay time models to determine optimal inspection policies for deteriorating infrastructures. We consider the case where complex infrastructures can fail due to different causes (defects) originating from various environmental or operational conditions, and capture this through modeling the arrival of different types of defects as nonhomogeneous Poisson processes with distinct rates of occurrence of defects. Additionally, we assume at each inspection epoch, there are multiple inspection methods available for use from which one is to be selected for use at that particular epoch. The key contribution that distinguishes our proposed models from previous works on delay time modeling is simultaneously considering multiple defect types and multiple inspection methods.

Two mixed-integer nonlinear programming models are introduced to address the problem described above. The first model focuses on determining the optimal inspection policy that maximizes the reliability of the system over its useful life subject to a minimal threshold value of this reliability term. The second model determines the optimal policy that minimizes the system downtime. The two models are solved using a branch-and-cut global optimization approach. Two separate numerical studies are conducted to demonstrate the performance of the models and validate it through benchmarking these results against a prior study in the literature.

Autors: Mohamad Mahmoudi;Alaa Elwany;Kamran Shahanaghi;Mohammad Reza Gholamian;
Appeared in: IEEE Transactions on Reliability
Publication date: Dec 2017, volume: 66, issue:4, pages: 1073 - 1084
Publisher: IEEE
 
» A Dictionary Learning-Based 3D Morphable Shape Model
Abstract:
Face analysis from 2D images and videos is a central task in many multimedia applications. Methods developed to this end perform either face recognition or facial expression recognition, and in both cases results are negatively influenced by variations in pose, illumination, and resolution of the face. Such variations have a lower impact on 3D face data, which has given the way to the idea of using a 3D morphable model as an intermediate tool to enhance face analysis on 2D data. In this paper, we propose a new approach for constructing a 3D morphable shape model (called DL-3DMM) and show our solution can reach the accuracy of deformation required in applications where fine details of the face are concerned. For constructing the model, we start from a set of 3D face scans with large variability in terms of ethnicity and expressions. Across these training scans, we compute a point-to-point dense alignment, which is accurate also in the presence of topological variations of the face. The DL-3DMM is constructed by learning a dictionary of basis components on the aligned scans. The model is then fitted to 2D target faces using an efficient regularized ridge-regression guided by 2D/3D facial landmark correspondences in order to generate pose-normalized face images. Comparison between the DL-3DMM and the standard PCA-based 3DMM demonstrates that in general a lower reconstruction error can be obtained with our solution. Application to action unit detection and emotion recognition from 2D images and videos shows competitive results with state of the art methods on two benchmark datasets.
Autors: Claudio Ferrari;Giuseppe Lisanti;Stefano Berretti;Alberto Del Bimbo;
Appeared in: IEEE Transactions on Multimedia
Publication date: Dec 2017, volume: 19, issue:12, pages: 2666 - 2679
Publisher: IEEE
 
» A Differential Chaotic Bit-Interleaved Coded Modulation System Over Multipath Rayleigh Channels
Abstract:
In this paper, a novel differential chaotic bit-interleaved coded modulation (DC-BICM) system is proposed for band-limited transmission. This system combines protograph-based low density parity check codes with constellation-based -ary differential chaos shift keying (DCSK) modulation by one bitwise interleaving. Bit error rate simulation results show that the system has higher coding gain compared with the constellation-based -ary DCSK modulation system with the same spectral efficiency over multipath Rayleigh fading channels. At the same time, several simulations and P-EXIT analysis are used to analyze the performance of the proposed system. It is found that there is a lot of room for optimization of the system by comparing decoding thresholds and simulation results. Moreover, the system with only partial channel state information has better performance and lower complexity compared with the traditional bit-interleaved coded modulation (BICM) direct-sequence-spread-spectrum system. As a result, the DC-BICM system is a good candidate for band-limited transmission.
Autors: Jia Zhan;Lin Wang;Marcos Katz;Guanrong Chen;
Appeared in: IEEE Transactions on Communications
Publication date: Dec 2017, volume: 65, issue:12, pages: 5257 - 5265
Publisher: IEEE
 
» A Diffusion Filter Based Scheme to Denoise Seismic Attributes and Improve Predicted Porosity Volume
Abstract:
This paper proposes a diffusion filter based scheme to denoise seismic attributes and to improve the porosity volume, which is predicted from seismic attributes. We compare the performances of multiple diffusion [such as Perona–Malik diffusion filter, complex diffusion filter, improved complex adaptive diffusion filter (ICADF)] and nondiffusion (such as two-dimensional (2-D) median, 3-D median, smoothing, and bilateral filter) based filters in terms of four metrics such as root mean square error (RMSE), normalized RMSE, signal to noise ratio (SNR), and peak SNR (PSNR). In our earlier publication, we used an artificial neural network (ANN) to predict a lithological property (sand fraction) over a study area. We trained the ANN using an integrated dataset of low-resolution seismic attributes and a limited number of high-resolution well logs. In this paper, we generate the porosity volume from the seismic attributes using an ANN. The predicted porosity logs contain irregularities and artifacts due to the nonlinear mapping of the learning algorithm (e.g., ANN). We apply a set of filters to the output of the ANN to regularize the predicted porosity volume. The filtered porosity logs are compared with the generated log. The ICADF has been found to be most suitable for denoising the seismic data and the porosity volume. Generation of porosity maps from seismic inputs would be helpful to petroleum engineers for reservoir characterization.
Autors: Soumi Chaki;Aurobinda Routray;William K. Mohanty;
Appeared in: IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing
Publication date: Dec 2017, volume: 10, issue:12, pages: 5265 - 5274
Publisher: IEEE
 
» A Distance-Based Approach to Strong Target Control of Dynamical Networks
Abstract:
This paper deals with controllability of dynamical networks. It is often unfeasible or unnecessary to fully control large-scale networks, which motivates the control of a prescribed subset of agents of the network. This specific form of output control is known under the name target control. We consider target control of a family of linear control systems associated with a network, and provide both a necessary and a sufficient topological condition under which the network is strongly targeted controllable. Furthermore, a leader selection algorithm is presented to compute leader sets achieving target control.
Autors: Henk J. van Waarde;M. Kanat Camlibel;Harry L. Trentelman;
Appeared in: IEEE Transactions on Automatic Control
Publication date: Dec 2017, volume: 62, issue:12, pages: 6266 - 6277
Publisher: IEEE
 
» A Distributed 1-bit Compressed Sensing Algorithm for Nonlinear Sensors With a Cramer–Rao Bound
Abstract:
A distributed 1-bit compressed sensing (CS) algorithm in a wireless sensor network with nonlinear sensors is proposed. In the context of 1-bit CS, the diffusion cooperation scheme is used with distributed implementation. Toward that end, a traditional steepest-descent solution is considered to minimize the appropriate global and local convex cost functions. Hence, a common parameter vector is optimally and cooperatively estimated solely from the sign of nonlinear measurements. A diffusion cooperation scheme is suggested for distributive learning of the vector in two scenarios. The first is the non-blind case, where the nonlinearity is known in advance. The second is the blind case, where the nonlinearity of sensors are unknown in advance. In addition, for the linear case, a Cramer-Rao bound for distributed 1-bit CS is derived and compared with the experimental results. Considering the nonlinear case, the proposed algorithm for the non-blind and blind cases is compared with the linear case. Simulation results show the efficacy of the proposed distributed algorithm and its robustness against nonlinearity of the sensors.
Autors: Hadi Zayyani;Rouhollah Sari;Mehdi Korki;
Appeared in: IEEE Communications Letters
Publication date: Dec 2017, volume: 21, issue:12, pages: 2626 - 2629
Publisher: IEEE
 
» A Dynamic Mode Decomposition Based Edge Detection Method for Art Images
Abstract:
Edge detection is a widely used feature extraction method in various fields, such as image processing, computer vision, machine vision, and so forth. However, it is still a challenging task to extract edges from art images, due to the false edge, shadow, and double lines of art images. In this paper, we propose a dynamic mode decomposition algorithm (DMD) based method for edge detection of art images. This is achieved by proposing a new color space based denoise method to deal with the shadow issue. Then, the false edge and double lines can be resolved by employing DMD method, which can be used to extract sparse features from the denoised images. Here, the sparse features have been enhanced by a new designed eight direction gradient operator. Finally, the effectiveness of our method will be demonstrated through detecting the edges of three classical types of art images (Comic, Oil Painting, and Printmaking).
Autors: Chongke Bi;Ye Yuan;Ronghui Zhang;Yiqing Xiang;Yuehuan Wang;Jiawan Zhang;
Appeared in: IEEE Photonics Journal
Publication date: Dec 2017, volume: 9, issue:6, pages: 1 - 13
Publisher: IEEE
 
» A Dynamic QoS Negotiation Mechanism Between Wired and Wireless SDN Domains
Abstract:
Flows in software defined networking (SDN) can pass through multiple domains having separate controllers. A domain is interpreted as part of the network topology under a SDN controller. This necessitates negotiation between various domains, to meet the QoS requirements of flows. These QoS negotiations may be static or dynamic. The SDN domains may be wired or wireless. Though, there have been efforts in the past to define inter-domain QoS negotiations for wired networks using SDN, to the best our knowledge, not much headway has been made when both wireless and wired domains are involved. In this paper, we consider a case where flows connect devices passing through a wired and a wireless domain having separate SDN controllers, and propose a novel QoS negotiation mechanism between them. First, we define a generic mechanism to map QoS parameters from one domain to the other. We then, define utilities for both the domains based on the QoS parameters of flows, and model our proposed mechanism as a mixed integer program. We observe that the problem is NP-complete, and propose a branch and bound-based algorithm to maximize the utility of the wireless domain, and evaluate the same for the wired part. Results indicate, as the resources provided to the flows in the wired domain varies dynamically, the wireless domain accordingly modifies the flows, satisfying their minimum/maximum QoS requirements under different scenarios. Conversely, this also means that resources in wired domain get adjusted, when wireless counterpart changes flow parameters based on wireless channel conditions. Further, the results reveal that smaller granularity of increment/decrement steps of QoS parameters satisfy flow requirements efficiently.
Autors: Dibakar Das;Jyotsna Bapat;Debabrata Das;
Appeared in: IEEE Transactions on Network and Service Management
Publication date: Dec 2017, volume: 14, issue:4, pages: 1076 - 1085
Publisher: IEEE
 

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