Details, datasheet, quote on part number: TDA8043K
PartTDA8043K
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Description
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Features, Applications

Preliminary specification File under Integrated Circuits, IC02 1997 Feb 25

FEATURES One chip Digital Video Broadcasting (DVB) compliant demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer 3.3 V supply voltage (up 5 V allowed) Internal clock divider On-chip crystal oscillator QPSK/BPSK demodulator: Interpolator to handle variable symbol rates without an external anti-aliasing filter On-chip Automatic Gain Control (AGC) of the analog input I and Q baseband signals or tuner AGC control Two on-chip matched A/D converters (7 bits) Square-Root Raised-Cosine Nyquist filter with programmable roll-off factor High maximum symbol frequency: 32 Msymbols/s Can be used at low channel Es/No (Symbol energy-to-noise ratio) Internal carrier recovery, clock recovery and AGC loops with programmable loop filters Two carrier recovery loops enabling phase tracking of the incoming symbols Different modulation schemes: Quarter Phase Shift Keying (QPSK) and Bi-phase Shift Keying (BPSK) Signal-to-noise ratio (S/R) estimation External indication of demodulator lock Viterbi decoder: Rate 1/2 convolutional code based Constraint length = 7 with = 171oct and 133oct Supported puncturing code rates: and bit inputs for `soft decision' for both I and Q Truncation length: 144 Automatic synchronization Channel BER (Bit Error Rate) estimation External indication of Viterbi sync lock Differential decoding supported Reed Solomon (RS) decoder: = 8) Reed Solomon code

Automatic (I2C-bus configurable) synchronization of bytes, transport packets and frames Internal convolutional de-interleaving = 12; using internal memory) De-randomizer based on Pseudo Random Binary Sequence (PRBS) External indication of RS decoder sync lock External indication of uncorrectable errors (transport error indicator is set) Indication of the number of lost blocks Indication of the number of corrected blocks/bytes I2C-bus interface: I2C-bus interface initializes and monitors the demodulator and Forward Error Correction (FEC) decoder with stand-by mode; when I2C-bus is used, default mode is defined 4 bits I/O expander for flexible access to and from the I2C-bus Package: PLCC84 Boundary scan test. APPLICATIONS Demodulation and error correction for digital satellite TV.

GENERAL DESCRIPTION This document specifies a DVB compliant demodulator and error correction decoder IC for reception of QPSK and BPSK modulated signals for satellite applications. The SDD (Satellite Demodulator and Decoder) can handle variable symbol rates without adapting the analog filters within the tuner. Typical applications for this device are: Single-cast: one QPSK/BPSK modulated signal in a single channel Multi-cast: two or more QPSK/BPSK modulated signals in a single channel Simul-cast: QPSK/BPSK modulated signal together with a Frequency Modulated (FM) signal in a single channel. The SDD requires the two I and Q analog quadrature demodulated baseband signals as an input and provides 8-bit wide MPEG2 transport packet data at the output. The output of the SDD can be directly connected to the descrambler (SAA7206) or the demultiplexer (SAA7205). QUICK REFERENCE DATA SYMBOL VDDA VDDD IDD fclk rs IL Ptot Tstg Tamb Tj S/N Notes 1. This implementation was measured in a laboratory environment. 2. These values are specified for a symbol rate of 27.5 MSymbols/s. ORDERING INFORMATION TYPE NUMBER TDA8043K 1997 Feb 25 PACKAGE NAME PLCC84 DESCRIPTION plastic leaded chip carrier; 84 leads 3 PARAMETER analog supply voltage digital supply voltage supply current clock frequency symbol rate implementation loss Nyquist roll-off (programmable) total power dissipation storage temperature operating ambient temperature operating junction temperature signal-to-noise ratio for locking the SDD (QPSK) Tamb = 70C Tamb = 70C; note 2 note 2 VDD 3.3 V; note 2 CONDITIONS(1) MIN. tbf TYP.

The output can also be used to monitor internal data, for example I/Q after demodulation, data after Viterbi decoding and data after de-interleaving. The SDD requires a single clock frequency which is independent to the received symbol rate as long as the clock frequency is slightly higher than twice the highest symbol frequency. This makes it possible to use a clock signal which already exists within the complete system. All loops to recover the data from the received symbols are internal. No external loop components are required. Loop parameters for the clock and carrier recovery can be controlled by I2C-bus. The SDD can be controlled and monitored An I2C-bus default mode is specified which makes it possible to use the device with a minimum of software control. A 4-bit bidirectional I/O expander and an interrupt line is available. By sending an interrupt signal, the SDD can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus.


 

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